mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-18 17:34:57 +00:00
Implemented unaligned stores in live generator, begin improving error handling in live generator
This commit is contained in:
Mr-Wiseguy
parent
aa765c435f
commit
3672805121
2 changed files with 175 additions and 38 deletions
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@ -66,6 +66,7 @@ N64Recomp::LiveGenerator::LiveGenerator(size_t num_funcs, const LiveGeneratorInp
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compiler = sljit_create_compiler(nullptr);
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context = std::make_unique<LiveGeneratorContext>();
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context->func_labels.resize(num_funcs);
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errored = false;
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}
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N64Recomp::LiveGenerator::~LiveGenerator() {
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@ -177,6 +178,7 @@ N64Recomp::LiveGeneratorOutput N64Recomp::LiveGenerator::finish() {
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sljit_free_compiler(compiler);
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compiler = nullptr;
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errored = false;
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return ret;
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}
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@ -212,6 +214,7 @@ constexpr int get_fpr_double_context_offset(int fpr_index) {
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constexpr int get_fpr_u32l_context_offset(int fpr_index) {
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if (fpr_index & 1) {
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// TODO implement odd floats.
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assert(false);
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return -1;
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// return fmt::format("ctx->f_odd[({} - 1) * 2]", fpr_index);
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@ -236,7 +239,7 @@ void get_gpr_values(int gpr, sljit_sw& out, sljit_sw& outw) {
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}
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}
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void get_operand_values(N64Recomp::Operand operand, const N64Recomp::InstructionContext& context, sljit_sw& out, sljit_sw& outw) {
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bool get_operand_values(N64Recomp::Operand operand, const N64Recomp::InstructionContext& context, sljit_sw& out, sljit_sw& outw) {
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using namespace N64Recomp;
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bool relocation_valid = false;
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@ -288,13 +291,13 @@ void get_operand_values(N64Recomp::Operand operand, const N64Recomp::Instruction
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break;
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case Operand::FdU32H:
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assert(false);
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break;
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return false;
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case Operand::FsU32H:
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assert(false);
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break;
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return false;
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case Operand::FtU32H:
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assert(false);
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break;
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return false;
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case Operand::FdU64:
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out = SLJIT_MEM1(Registers::ctx);
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outw = get_fpr_u64_context_offset(context.fd);
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@ -340,6 +343,7 @@ void get_operand_values(N64Recomp::Operand operand, const N64Recomp::Instruction
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outw = 0;
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break;
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}
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return true;
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}
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bool outputs_to_zero(N64Recomp::Operand output, const N64Recomp::InstructionContext& ctx) {
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@ -361,23 +365,36 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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return;
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}
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bool failed = false;
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sljit_sw dst;
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sljit_sw dstw;
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sljit_sw src1;
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sljit_sw src1w;
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sljit_sw src2;
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sljit_sw src2w;
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get_operand_values(op.output, ctx, dst, dstw);
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get_operand_values(op.operands.operands[0], ctx, src1, src1w);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w);
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bool output_good = get_operand_values(op.output, ctx, dst, dstw);
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bool input0_good = get_operand_values(op.operands.operands[0], ctx, src1, src1w);
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bool input1_good = get_operand_values(op.operands.operands[1], ctx, src2, src2w);
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if (!output_good || !input0_good || !input1_good) {
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assert(false);
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errored = true;
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return;
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}
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// If a relocation is present, perform the relocation and change src1/src1w to use the relocated value.
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if (ctx.reloc_type != RelocType::R_MIPS_NONE) {
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// Only allow LO16 relocations.
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assert(ctx.reloc_type == RelocType::R_MIPS_LO16);
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if (ctx.reloc_type != RelocType::R_MIPS_LO16) {
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assert(false);
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errored = true;
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return;
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}
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// Only allow relocations on immediates.
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assert(src2 == SLJIT_IMM);
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if (src2 != SLJIT_IMM) {
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assert(false);
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errored = true;
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return;
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}
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// Only allow relocations on loads and adds.
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switch (op.type) {
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case BinaryOpType::LD:
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@ -397,6 +414,8 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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default:
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// Relocations aren't allowed on this instruction.
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assert(false);
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errored = true;
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return;
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}
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// Load the relocated address into temp2.
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load_relocated_address(ctx, Registers::arithmetic_temp1);
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@ -408,14 +427,24 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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}
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// TODO validate that the unary ops are valid for the current binary op.
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assert(op.operands.operand_operations[0] == UnaryOpType::None ||
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op.operands.operand_operations[0] == UnaryOpType::ToU64 ||
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op.operands.operand_operations[0] == UnaryOpType::ToS64 ||
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op.operands.operand_operations[0] == UnaryOpType::ToU32);
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if (op.operands.operand_operations[0] != UnaryOpType::None &&
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op.operands.operand_operations[0] != UnaryOpType::ToU64 &&
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op.operands.operand_operations[0] != UnaryOpType::ToS64 &&
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op.operands.operand_operations[0] != UnaryOpType::ToU32)
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{
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assert(false);
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errored = true;
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return;
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}
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assert(op.operands.operand_operations[1] == UnaryOpType::None ||
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op.operands.operand_operations[1] == UnaryOpType::Mask5 || // Only for 32-bit shifts
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op.operands.operand_operations[1] == UnaryOpType::Mask6); // Only for 64-bit shifts
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if (op.operands.operand_operations[1] != UnaryOpType::None &&
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op.operands.operand_operations[1] != UnaryOpType::Mask5 && // Only for 32-bit shifts
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op.operands.operand_operations[1] != UnaryOpType::Mask6) // Only for 64-bit shifts
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{
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assert(false);
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errored = true;
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return;
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}
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bool cmp_unsigned = op.operands.operand_operations[0] != UnaryOpType::ToS64;
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@ -439,7 +468,7 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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sljit_emit_fop2(this->compiler, op, dst, dstw, src1, src1w, src2, src2w);
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};
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auto do_load_op = [dst, dstw, src1, src1w, src2, src2w, &ctx, &failed, this](sljit_s32 op, int address_xor) {
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auto do_load_op = [dst, dstw, src1, src1w, src2, src2w, &ctx, this](sljit_s32 op, int address_xor) {
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// TODO 0 immediate optimization.
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// Add the base and immediate into the arithemtic temp.
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@ -457,7 +486,7 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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sljit_emit_op1(compiler, SLJIT_MOV, dst, dstw, Registers::arithmetic_temp1, 0);
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};
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auto do_compare_op = [cmp_unsigned, dst, dstw, src1, src1w, src2, src2w, &ctx, &failed, this](sljit_s32 op_unsigned, sljit_s32 op_signed) {
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auto do_compare_op = [cmp_unsigned, dst, dstw, src1, src1w, src2, src2w, &ctx, this](sljit_s32 op_unsigned, sljit_s32 op_signed) {
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// Pick the operation based on the signedness of the comparison.
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sljit_s32 op = cmp_unsigned ? op_unsigned : op_signed;
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@ -706,10 +735,9 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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break;
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default:
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assert(false);
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break;
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errored = true;
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return;
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}
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assert(!failed);
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}
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int32_t do_round_w_s(float num) {
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@ -784,19 +812,27 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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sljit_sw dstw;
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sljit_sw src;
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sljit_sw srcw;
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get_operand_values(op.output, ctx, dst, dstw);
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get_operand_values(op.input, ctx, src, srcw);
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bool output_good = get_operand_values(op.output, ctx, dst, dstw);
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bool input_good = get_operand_values(op.input, ctx, src, srcw);
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if (!output_good || !input_good) {
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assert(false);
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errored = true;
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return;
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}
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// If a relocation is needed for the input operand, perform the relocation and store the result directly.
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if (ctx.reloc_type != RelocType::R_MIPS_NONE) {
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// Only allow relocation of lui with an immediate.
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if (op.operation != UnaryOpType::Lui || op.input != Operand::ImmU16) {
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assert(false);
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errored = true;
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return;
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}
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// Only allow HI16 relocs.
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if (ctx.reloc_type != RelocType::R_MIPS_HI16) {
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assert(false);
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errored = true;
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return;
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}
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// Load the relocated address into temp1.
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@ -872,7 +908,8 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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switch (op.operation) {
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case UnaryOpType::Lui:
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if (src != SLJIT_IMM) {
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failed = true;
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assert(false);
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errored = true;
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break;
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}
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src = SLJIT_IMM;
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@ -1008,6 +1045,7 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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case UnaryOpType::Mask5:
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case UnaryOpType::Mask6:
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assert(false && "Unsupported unary op");
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errored = true;
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return;
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}
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@ -1020,8 +1058,6 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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else {
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sljit_emit_op1(compiler, jit_op, dst, dstw, src, srcw);
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}
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assert(!failed);
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}
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void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const InstructionContext& ctx) const {
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@ -1032,7 +1068,11 @@ void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const Instruc
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get_operand_values(op.value_input, ctx, src, srcw);
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// Only LO16 relocs are valid on stores.
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assert(ctx.reloc_type == RelocType::R_MIPS_NONE || ctx.reloc_type == RelocType::R_MIPS_LO16);
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if (ctx.reloc_type != RelocType::R_MIPS_NONE && ctx.reloc_type != RelocType::R_MIPS_LO16) {
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assert(false);
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errored = true;
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return;
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}
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if (ctx.reloc_type == RelocType::R_MIPS_LO16) {
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// Load the relocated address into temp1.
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@ -1043,10 +1083,82 @@ void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const Instruc
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sljit_emit_op2(compiler, SLJIT_ADD, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0, SLJIT_MEM1(Registers::ctx), get_gpr_context_offset(ctx.rs));
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}
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else {
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// TODO 0 immediate optimization.
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// Add the base register (rs) and the immediate to get the address and store it in the arithemtic temp.
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sljit_emit_op2(compiler, SLJIT_ADD, Registers::arithmetic_temp1, 0, SLJIT_MEM1(Registers::ctx), get_gpr_context_offset(ctx.rs), SLJIT_IMM, imm);
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}
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auto do_unaligned_store_op = [src, srcw, this](bool left, bool doubleword) {
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// Determine the shift direction to use for calculating the mask and shifting the loaded value.
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sljit_sw shift_op = left ? SLJIT_LSHR : SLJIT_SHL;
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// Determine the operation's word size.
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sljit_sw word_size = doubleword ? 8 : 4;
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// Mask the address with the alignment mask to get the misalignment and put it in temp2.
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// misalignment = addr & (word_size - 1);
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sljit_emit_op2(compiler, SLJIT_AND, Registers::arithmetic_temp2, 0, Registers::arithmetic_temp1, 0, SLJIT_IMM, word_size - 1);
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// Mask the address with ~alignment_mask to get the aligned address and put it in temp1.
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// addr = addr & ~(word_size - 1);
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sljit_emit_op2(compiler, SLJIT_AND, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0, SLJIT_IMM, ~(word_size - 1));
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// Load the word at rdram + aligned address into the temp1 with sign-extension.
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// loaded_value = *addr
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if (doubleword) {
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// Rotate the loaded doubleword by 32 bits to swap the two words into the right order.
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sljit_emit_op2(compiler, SLJIT_ROTL, Registers::arithmetic_temp3, 0, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0, SLJIT_IMM, 32);
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}
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else {
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// Use MOV_S32 to sign-extend the loaded word.
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sljit_emit_op1(compiler, SLJIT_MOV_S32, Registers::arithmetic_temp3, 0, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0);
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}
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// Inverse the misalignment if this is a right load.
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if (!left) {
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// misalignment = (word_size - 1 - misalignment) * 8
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sljit_emit_op2(compiler, SLJIT_SUB, Registers::arithmetic_temp2, 0, SLJIT_IMM, word_size - 1, Registers::arithmetic_temp2, 0);
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}
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// Calculate the misalignment shift and put it into temp2.
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// misalignment_shift = misalignment * 8
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sljit_emit_op2(compiler, SLJIT_SHL, Registers::arithmetic_temp2, 0, Registers::arithmetic_temp2, 0, SLJIT_IMM, 3);
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// Shift the input value by the misalignment shift and put it into temp4.
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// input_value SHIFT= misalignment_shift
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sljit_emit_op2(compiler, shift_op, Registers::arithmetic_temp4, 0, src, srcw, Registers::arithmetic_temp2, 0);
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// Calculate the misalignment mask and put it into temp2. Use a 32-bit shift if this is a 32-bit operation.
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// misalignment_mask = word(-1) SHIFT misalignment_shift
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sljit_emit_op2(compiler, doubleword ? shift_op : (shift_op | SLJIT_32),
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Registers::arithmetic_temp2, 0,
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SLJIT_IMM, doubleword ? uint64_t(-1) : uint32_t(-1),
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Registers::arithmetic_temp2, 0);
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// Mask the input value with the misalignment mask and place it into temp4.
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// masked_value = shifted_value & misalignment_mask
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sljit_emit_op2(compiler, SLJIT_AND, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp2, 0);
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// Invert the misalignment mask and store it into temp2.
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// misalignment_mask = ~misalignment_mask
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sljit_emit_op2(compiler, SLJIT_XOR, Registers::arithmetic_temp2, 0, Registers::arithmetic_temp2, 0, SLJIT_IMM, sljit_sw(-1));
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// Mask the loaded value by the misalignment mask.
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// input_value &= misalignment_mask
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sljit_emit_op2(compiler, SLJIT_AND, Registers::arithmetic_temp3, 0, Registers::arithmetic_temp3, 0, Registers::arithmetic_temp2, 0);
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// Combine the masked initial value with the shifted loaded value and store it in the destination.
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// out = masked_value | input_value
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if (doubleword) {
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// Combine the values into a temp so that it can be rotated to the correct word order.
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sljit_emit_op2(compiler, SLJIT_OR, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp3, 0);
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sljit_emit_op2(compiler, SLJIT_ROTL, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0, Registers::arithmetic_temp4, 0, SLJIT_IMM, 32);
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}
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else {
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sljit_emit_op2(compiler, SLJIT_OR32, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp3, 0);
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}
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};
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switch (op.type) {
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case StoreOpType::SD:
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case StoreOpType::SDC1:
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@ -1054,10 +1166,10 @@ void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const Instruc
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sljit_emit_op2(compiler, SLJIT_ROTL, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0, src, srcw, SLJIT_IMM, 32);
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break;
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case StoreOpType::SDL:
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assert(false);
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do_unaligned_store_op(true, true);
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break;
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case StoreOpType::SDR:
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assert(false);
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do_unaligned_store_op(false, true);
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break;
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case StoreOpType::SW:
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case StoreOpType::SWC1:
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@ -1065,10 +1177,10 @@ void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const Instruc
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sljit_emit_op1(compiler, SLJIT_MOV_U32, SLJIT_MEM2(Registers::rdram, Registers::arithmetic_temp1), 0, src, srcw);
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break;
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case StoreOpType::SWL:
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assert(false);
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do_unaligned_store_op(true, false);
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break;
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case StoreOpType::SWR:
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assert(false);
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do_unaligned_store_op(false, false);
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break;
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case StoreOpType::SH:
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// xor the address with 2
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@ -1135,6 +1247,7 @@ void N64Recomp::LiveGenerator::emit_function_call_by_register(int reg) const {
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void N64Recomp::LiveGenerator::emit_function_call_reference_symbol(const Context& context, uint16_t section_index, size_t symbol_index) const {
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const N64Recomp::ReferenceSymbol& sym = context.get_reference_symbol(section_index, symbol_index);
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assert(false);
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errored = true;
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}
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void N64Recomp::LiveGenerator::emit_function_call(const Context& recompiler_context, size_t function_index) const {
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@ -1182,11 +1295,24 @@ void N64Recomp::LiveGenerator::emit_jtbl_addend_declaration(const JumpTable& jtb
|
|||
|
||||
void N64Recomp::LiveGenerator::emit_branch_condition(const ConditionalBranchOp& op, const InstructionContext& ctx) const {
|
||||
// Make sure there's no pending jump.
|
||||
assert(context->cur_branch_jump == nullptr);
|
||||
if(context->cur_branch_jump != nullptr) {
|
||||
assert(false);
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
|
||||
// Branch conditions do not allow unary ops, except for ToS64 on the first operand to indicate the branch comparison is signed.
|
||||
assert(op.operands.operand_operations[0] == UnaryOpType::None || op.operands.operand_operations[0] == UnaryOpType::ToS64);
|
||||
assert(op.operands.operand_operations[1] == UnaryOpType::None);
|
||||
if(op.operands.operand_operations[0] != UnaryOpType::None && op.operands.operand_operations[0] != UnaryOpType::ToS64) {
|
||||
assert(false);
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
|
||||
if (op.operands.operand_operations[1] != UnaryOpType::None) {
|
||||
assert(false);
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
|
||||
sljit_s32 condition_type;
|
||||
bool cmp_signed = op.operands.operand_operations[0] == UnaryOpType::ToS64;
|
||||
|
|
@ -1233,6 +1359,8 @@ void N64Recomp::LiveGenerator::emit_branch_condition(const ConditionalBranchOp&
|
|||
break;
|
||||
default:
|
||||
assert(false && "Invalid branch condition comparison operation!");
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
sljit_sw src1;
|
||||
sljit_sw src1w;
|
||||
|
|
@ -1243,7 +1371,11 @@ void N64Recomp::LiveGenerator::emit_branch_condition(const ConditionalBranchOp&
|
|||
get_operand_values(op.operands.operands[1], ctx, src2, src2w);
|
||||
|
||||
// Relocations aren't valid on conditional branches.
|
||||
assert(ctx.reloc_type == RelocType::R_MIPS_NONE);
|
||||
if(ctx.reloc_type != RelocType::R_MIPS_NONE) {
|
||||
assert(false);
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
|
||||
// Create a compare jump and track it as the pending branch jump.
|
||||
context->cur_branch_jump = sljit_emit_cmp(compiler, condition_type, src1, src1w, src2, src2w);
|
||||
|
|
@ -1251,7 +1383,11 @@ void N64Recomp::LiveGenerator::emit_branch_condition(const ConditionalBranchOp&
|
|||
|
||||
void N64Recomp::LiveGenerator::emit_branch_close() const {
|
||||
// Make sure there's a pending branch jump.
|
||||
assert(context->cur_branch_jump != nullptr);
|
||||
if(context->cur_branch_jump == nullptr) {
|
||||
assert(false);
|
||||
errored = true;
|
||||
return;
|
||||
}
|
||||
|
||||
// Assign a label at this point to the pending branch jump and clear it.
|
||||
sljit_set_label(context->cur_branch_jump, sljit_emit_label(compiler));
|
||||
|
|
|
|||
|
|
@ -108,6 +108,7 @@ namespace N64Recomp {
|
|||
sljit_compiler* compiler;
|
||||
LiveGeneratorInputs inputs;
|
||||
mutable std::unique_ptr<LiveGeneratorContext> context;
|
||||
mutable bool errored;
|
||||
};
|
||||
|
||||
void live_recompiler_init();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue