mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-24 12:24:59 +00:00
Implemented SP, DP, and SI events
Inject a thread pause into infinite loops to allow the idle thread to yield for event processing Removed all preemption usage from the scheduler
This commit is contained in:
Mr-Wiseguy
parent
b94fe6f5fb
commit
39b67c8468
20 changed files with 449 additions and 113 deletions
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@ -318,7 +318,13 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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break;
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case InstrId::cpu_j:
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case InstrId::cpu_b:
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print_unconditional_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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{
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uint32_t branch_target = instr.getBranchVramGeneric();
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if (branch_target == instr_vram) {
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print_line("void pause_self(uint8_t *rdram); pause_self(rdram)");
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}
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print_unconditional_branch("goto L_{:08X}", branch_target);
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}
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break;
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case InstrId::cpu_jr:
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if (rs == (int)rabbitizer::Registers::Cpu::GprO32::GPR_O32_ra) {
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@ -422,6 +428,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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if ((ft & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = MEM_W({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("NAN_CHECK(ctx->f{}.fl)", ft);
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} else {
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// odd fpr
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print_line("ctx->f{}.u32h = MEM_W({:#X}, {}{})", ft - 1, (int16_t)imm, ctx_gpr_prefix(base), base);
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@ -429,7 +436,8 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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break;
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case InstrId::cpu_ldc1:
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if ((ft & 1) == 0) {
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print_line("ctx->f{}.u64 = MEM_D({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("ctx->f{}.u64 = LD({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("NAN_CHECK(ctx->f{}.d)", ft);
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} else {
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fmt::print(stderr, "Invalid operand for ldc1: f{}\n", ft);
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return false;
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@ -446,7 +454,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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break;
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case InstrId::cpu_sdc1:
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if ((ft & 1) == 0) {
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print_line("MEM_D({:#X}, {}{}) = ctx->f{}.u64", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
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print_line("SD(ctx->f{}.u64, {:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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} else {
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fmt::print(stderr, "Invalid operand for sdc1: f{}\n", ft);
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return false;
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@ -525,6 +533,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_mov_s:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl)", fs);
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print_line("ctx->f{}.fl = ctx->f{}.fl", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for mov.s: f{} f{}\n", fd, fs);
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@ -534,6 +543,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_mov_d:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d)", fs);
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print_line("ctx->f{}.d = ctx->f{}.d", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for mov.d: f{} f{}\n", fd, fs);
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@ -543,6 +553,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_neg_s:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl)", fs);
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print_line("ctx->f{}.fl = -ctx->f{}.fl", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for neg.s: f{} f{}\n", fd, fs);
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@ -552,6 +563,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_neg_d:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d)", fs);
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print_line("ctx->f{}.d = -ctx->f{}.d", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for neg.d: f{} f{}\n", fd, fs);
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@ -561,6 +573,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_abs_s:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl)", fs);
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print_line("ctx->f{}.fl = fabsf(ctx->f{}.fl)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for abs.s: f{} f{}\n", fd, fs);
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@ -570,6 +583,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_abs_d:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d)", fs);
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print_line("ctx->f{}.d = fabs(ctx->f{}.d)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for abs.d: f{} f{}\n", fd, fs);
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@ -579,6 +593,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_sqrt_s:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl)", fs);
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print_line("ctx->f{}.fl = sqrtf(ctx->f{}.fl)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for sqrt.s: f{} f{}\n", fd, fs);
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@ -588,6 +603,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_sqrt_d:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d)", fs);
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print_line("ctx->f{}.d = sqrt(ctx->f{}.d)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for sqrt.d: f{} f{}\n", fd, fs);
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@ -597,6 +613,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_add_s:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl); NAN_CHECK(ctx->f{}.fl)", fs, ft);
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print_line("ctx->f{}.fl = ctx->f{}.fl + ctx->f{}.fl", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for add.s: f{} f{} f{}\n", fd, fs, ft);
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@ -606,6 +623,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_add_d:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d); NAN_CHECK(ctx->f{}.d)", fs, ft);
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print_line("ctx->f{}.d = ctx->f{}.d + ctx->f{}.d", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for add.d: f{} f{} f{}\n", fd, fs, ft);
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@ -615,6 +633,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_sub_s:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl); NAN_CHECK(ctx->f{}.fl)", fs, ft);
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print_line("ctx->f{}.fl = ctx->f{}.fl - ctx->f{}.fl", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for sub.s: f{} f{} f{}\n", fd, fs, ft);
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@ -624,6 +643,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_sub_d:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d); NAN_CHECK(ctx->f{}.d)", fs, ft);
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print_line("ctx->f{}.d = ctx->f{}.d - ctx->f{}.d", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for sub.d: f{} f{} f{}\n", fd, fs, ft);
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@ -633,6 +653,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_mul_s:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl); NAN_CHECK(ctx->f{}.fl)", fs, ft);
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print_line("ctx->f{}.fl = MUL_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for mul.s: f{} f{} f{}\n", fd, fs, ft);
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@ -642,6 +663,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_mul_d:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d); NAN_CHECK(ctx->f{}.d)", fs, ft);
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print_line("ctx->f{}.d = MUL_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for mul.d: f{} f{} f{}\n", fd, fs, ft);
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@ -651,6 +673,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_div_s:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl); NAN_CHECK(ctx->f{}.fl)", fs, ft);
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print_line("ctx->f{}.fl = DIV_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for div.s: f{} f{} f{}\n", fd, fs, ft);
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@ -660,6 +683,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_div_d:
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if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d); NAN_CHECK(ctx->f{}.d)", fs, ft);
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print_line("ctx->f{}.d = DIV_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
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} else {
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fmt::print(stderr, "Invalid operand(s) for div.d: f{} f{} f{}\n", fd, fs, ft);
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@ -687,6 +711,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_cvt_d_s:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.fl)", fs);
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print_line("ctx->f{}.d = CVT_D_S(ctx->f{}.fl)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for cvt.d.s: f{} f{}\n", fd, fs);
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@ -696,6 +721,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_cvt_s_d:
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if ((fd & 1) == 0 && (fs & 1) == 0) {
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// even fpr
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print_line("NAN_CHECK(ctx->f{}.d)", fs);
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print_line("ctx->f{}.fl = CVT_S_D(ctx->f{}.d)", fd, fs);
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} else {
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fmt::print(stderr, "Invalid operand(s) for cvt.s.d: f{} f{}\n", fd, fs);
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