mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-24 12:24:59 +00:00
Implemented relocatable overlays (OoT runs)
This commit is contained in:
Mr-Wiseguy
parent
d2603ce07c
commit
602be9c2c6
8 changed files with 337 additions and 52 deletions
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@ -17,7 +17,8 @@ std::string_view ctx_gpr_prefix(int reg) {
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return "";
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}
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bool process_instruction(const RecompPort::Context& context, const RecompPort::Function& func, const RecompPort::FunctionStats& stats, const std::unordered_set<uint32_t>& skipped_insns, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely, std::span<std::vector<uint32_t>> static_funcs_out) {
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bool process_instruction(const RecompPort::Context& context, const RecompPort::Function& func, const RecompPort::FunctionStats& stats, const std::unordered_set<uint32_t>& skipped_insns, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, size_t reloc_index, bool& needs_link_branch, bool& is_branch_likely, std::span<std::vector<uint32_t>> static_funcs_out) {
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const auto& section = context.sections[func.section_index];
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const auto& instr = instructions[instr_index];
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needs_link_branch = false;
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is_branch_likely = false;
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@ -37,6 +38,40 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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return true;
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}
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bool at_reloc = false;
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bool reloc_handled = false;
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RecompPort::RelocType reloc_type = RecompPort::RelocType::R_MIPS_NONE;
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uint32_t reloc_section = 0;
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uint32_t reloc_target_section_offset = 0;
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// Check if this instruction has a reloc.
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if (section.relocatable && section.relocs[reloc_index].address == instr_vram) {
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// Get the reloc data for this instruction
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const auto& reloc = section.relocs[reloc_index];
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reloc_section = reloc.target_section;
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// Some symbols are in a nonexistent section (e.g. absolute symbols), so check that the section is valid before doing anything else.
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// Absolute symbols will never need to be relocated so it's safe to skip this.
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if (reloc_section < context.sections.size()) {
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// Check if the target section is also relocatable. References to symbols that are in a non-relocatable section don't need to
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// be relocated, so we can skip those.
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if (context.sections[reloc_section].relocatable) {
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// For games where references between sections aren't relocated, ignore this reloc if it points to a different section
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// TODO expose this as a config option
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// TODO!!!!! also relocate references to the corresponding bss section!!!!!
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if (reloc_section == func.section_index) {
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// Record the reloc's data.
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reloc_type = reloc.type;
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reloc_target_section_offset = reloc.target_address - context.sections[reloc_section].ram_addr;
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// Ignore all relocs that aren't HI16 or LO16.
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if (reloc_type == RecompPort::RelocType::R_MIPS_HI16 || reloc_type == RecompPort::RelocType::R_MIPS_LO16) {
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at_reloc = true;
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}
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}
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}
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}
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}
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auto print_indent = [&]() {
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fmt::print(output_file, " ");
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};
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@ -56,7 +91,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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if (instr_index < instructions.size() - 1) {
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bool dummy_needs_link_branch;
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bool dummy_is_branch_likely;
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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size_t next_reloc_index = reloc_index;
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uint32_t next_vram = instr_vram + 4;
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if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
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next_reloc_index++;
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}
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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}
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print_indent();
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fmt::print(output_file, fmt_str, args...);
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@ -72,7 +112,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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if (instr_index < instructions.size() - 1) {
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bool dummy_needs_link_branch;
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bool dummy_is_branch_likely;
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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size_t next_reloc_index = reloc_index;
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uint32_t next_vram = instr_vram + 4;
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if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
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next_reloc_index++;
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}
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, true, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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}
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fmt::print(output_file, " ");
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fmt::print(output_file, fmt_str, args...);
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@ -98,13 +143,34 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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uint16_t imm = instr.Get_immediate();
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std::string unsigned_imm_string;
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std::string signed_imm_string;
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if (!at_reloc) {
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unsigned_imm_string = fmt::format("{:#X}", imm);
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signed_imm_string = fmt::format("{:#X}", (int16_t)imm);
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} else {
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switch (reloc_type) {
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case RecompPort::RelocType::R_MIPS_HI16:
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unsigned_imm_string = fmt::format("RELOC_HI16({}, {:#X})", reloc_section, reloc_target_section_offset);
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signed_imm_string = "(int16_t)" + unsigned_imm_string;
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reloc_handled = true;
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break;
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case RecompPort::RelocType::R_MIPS_LO16:
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unsigned_imm_string = fmt::format("RELOC_LO16({}, {:#X})", reloc_section, reloc_target_section_offset);
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signed_imm_string = "(int16_t)" + unsigned_imm_string;
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reloc_handled = true;
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break;
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}
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}
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switch (instr.getUniqueId()) {
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case InstrId::cpu_nop:
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fmt::print(output_file, "\n");
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break;
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// Arithmetic
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case InstrId::cpu_lui:
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print_line("{}{} = S32({:#X} << 16)", ctx_gpr_prefix(rt), rt, imm);
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print_line("{}{} = S32({} << 16)", ctx_gpr_prefix(rt), rt, unsigned_imm_string);
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break;
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case InstrId::cpu_add:
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case InstrId::cpu_addu:
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@ -132,19 +198,19 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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break;
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case InstrId::cpu_addi:
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case InstrId::cpu_addiu:
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print_line("{}{} = ADD32({}{}, {:#X})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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print_line("{}{} = ADD32({}{}, {})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
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break;
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case InstrId::cpu_and:
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print_line("{}{} = {}{} & {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_andi:
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print_line("{}{} = {}{} & {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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print_line("{}{} = {}{} & {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
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break;
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case InstrId::cpu_or:
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print_line("{}{} = {}{} | {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_ori:
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print_line("{}{} = {}{} | {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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print_line("{}{} = {}{} | {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
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break;
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case InstrId::cpu_nor:
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print_line("{}{} = ~({}{} | {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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@ -153,7 +219,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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print_line("{}{} = {}{} ^ {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_xori:
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print_line("{}{} = {}{} ^ {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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print_line("{}{} = {}{} ^ {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
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break;
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case InstrId::cpu_sll:
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print_line("{}{} = S32({}{}) << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
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@ -177,13 +243,13 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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print_line("{}{} = SIGNED({}{}) < SIGNED({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_slti:
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print_line("{}{} = SIGNED({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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print_line("{}{} = SIGNED({}{}) < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
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break;
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case InstrId::cpu_sltu:
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print_line("{}{} = {}{} < {}{} ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sltiu:
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print_line("{}{} = {}{} < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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print_line("{}{} = {}{} < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
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break;
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case InstrId::cpu_mult:
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print_line("result = S64({}{}) * S64({}{}); lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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@ -207,29 +273,29 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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// Loads
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// TODO ld
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case InstrId::cpu_lw:
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print_line("{}{} = MEM_W({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = MEM_W({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lh:
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print_line("{}{} = MEM_H({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = MEM_H({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lb:
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print_line("{}{} = MEM_B({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = MEM_B({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lhu:
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print_line("{}{} = MEM_HU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = MEM_HU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lbu:
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print_line("{}{} = MEM_BU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = MEM_BU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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// Stores
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case InstrId::cpu_sw:
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print_line("MEM_W({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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print_line("MEM_W({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sh:
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print_line("MEM_H({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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print_line("MEM_H({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sb:
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print_line("MEM_B({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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print_line("MEM_B({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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// TODO lwl, lwr
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// examples:
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@ -246,20 +312,20 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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// LWR x + 2 -> 00000000 0189ABCD
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// LWR x + 3 -> FFFFFFFF 89ABCDEF
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case InstrId::cpu_lwl:
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print_line("{}{} = do_lwl(rdram, {:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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//print_line("{}{} = MEM_WL({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("{}{} = do_lwl(rdram, {}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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//print_line("{}{} = MEM_WL({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lwr:
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//print_line("{}{} = do_lwr(rdram, {:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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//print_line("//{}{} = MEM_WR({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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//print_line("{}{} = do_lwr(rdram, {}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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//print_line("//{}{} = MEM_WR({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_swl:
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print_line("do_swl(rdram, {:#X}, {}{}, {}{})", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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//print_line("MEM_WL({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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print_line("do_swl(rdram, {}, {}{}, {}{})", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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//print_line("MEM_WL({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_swr:
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//print_line("do_swr(rdram, {:#X}, {}{}, {}{})", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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//print_line("//MEM_WR({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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//print_line("do_swr(rdram, {}, {}{}, {}{})", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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//print_line("//MEM_WR({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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// Branches
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@ -356,7 +422,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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if (jtbl_find_result != stats.jump_tables.end()) {
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const RecompPort::JumpTable& cur_jtbl = *jtbl_find_result;
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bool dummy_needs_link_branch, dummy_is_branch_likely;
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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size_t next_reloc_index = reloc_index;
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uint32_t next_vram = instr_vram + 4;
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if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
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next_reloc_index++;
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}
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
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print_indent();
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fmt::print(output_file, "switch (jr_addend_{:08X} >> 2) {{\n", cur_jtbl.jr_vram);
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for (size_t entry_index = 0; entry_index < cur_jtbl.entries.size(); entry_index++) {
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@ -471,16 +542,16 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_lwc1:
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if ((ft & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = MEM_W({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("ctx->f{}.u32l = MEM_W({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
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print_line("NAN_CHECK(ctx->f{}.fl)", ft);
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} else {
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// odd fpr
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print_line("ctx->f{}.u32h = MEM_W({:#X}, {}{})", ft - 1, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("ctx->f{}.u32h = MEM_W({}, {}{})", ft - 1, signed_imm_string, ctx_gpr_prefix(base), base);
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}
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break;
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case InstrId::cpu_ldc1:
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if ((ft & 1) == 0) {
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print_line("ctx->f{}.u64 = LD({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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print_line("ctx->f{}.u64 = LD({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
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print_line("NAN_CHECK(ctx->f{}.d)", ft);
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} else {
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fmt::print(stderr, "Invalid operand for ldc1: f{}\n", ft);
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@ -490,15 +561,15 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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case InstrId::cpu_swc1:
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if ((ft & 1) == 0) {
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// even fpr
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print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32l", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
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print_line("MEM_W({}, {}{}) = ctx->f{}.u32l", signed_imm_string, ctx_gpr_prefix(base), base, ft);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32h", (int16_t)imm, ctx_gpr_prefix(base), base, ft - 1);
|
||||
print_line("MEM_W({}, {}{}) = ctx->f{}.u32h", signed_imm_string, ctx_gpr_prefix(base), base, ft - 1);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sdc1:
|
||||
if ((ft & 1) == 0) {
|
||||
print_line("SD(ctx->f{}.u64, {:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("SD(ctx->f{}.u64, {}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for sdc1: f{}\n", ft);
|
||||
return false;
|
||||
|
|
@ -955,6 +1026,9 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
int num_likely_branches = 0;
|
||||
bool needs_link_branch = false;
|
||||
bool in_likely_delay_slot = false;
|
||||
const auto& section = context.sections[func.section_index];
|
||||
bool needs_reloc = section.relocatable;
|
||||
size_t reloc_index = 0;
|
||||
for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
|
||||
bool had_link_branch = needs_link_branch;
|
||||
bool is_branch_likely = false;
|
||||
|
|
@ -967,8 +1041,16 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
fmt::print(output_file, "L_{:08X}:\n", *cur_label);
|
||||
++cur_label;
|
||||
}
|
||||
|
||||
// If this is a relocatable section, advance the reloc index until we reach the last one or until we get to/pass the current instruction
|
||||
if (needs_reloc) {
|
||||
while (reloc_index < (section.relocs.size() - 1) && section.relocs[reloc_index].address < vram) {
|
||||
reloc_index++;
|
||||
}
|
||||
}
|
||||
|
||||
// Process the current instruction and check for errors
|
||||
if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
|
||||
if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, reloc_index, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
|
||||
fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path);
|
||||
output_file.clear();
|
||||
return false;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue