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https://github.com/N64Recomp/N64Recomp.git
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Implemented function stubbing
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Mr-Wiseguy
parent
fba0085946
commit
7df3e28c76
4 changed files with 99 additions and 78 deletions
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@ -997,91 +997,94 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
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" int c1cs = 0; \n", // cop1 conditional signal
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func.name);
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// Use a set to sort and deduplicate labels
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std::set<uint32_t> branch_labels;
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instructions.reserve(func.words.size());
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// Skip analysis and recompilation of this function is stubbed.
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if (!func.stubbed) {
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// Use a set to sort and deduplicate labels
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std::set<uint32_t> branch_labels;
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instructions.reserve(func.words.size());
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// First pass, disassemble each instruction and collect branch labels
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uint32_t vram = func.vram;
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for (uint32_t word : func.words) {
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const auto& instr = instructions.emplace_back(byteswap(word), vram);
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// First pass, disassemble each instruction and collect branch labels
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uint32_t vram = func.vram;
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for (uint32_t word : func.words) {
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const auto& instr = instructions.emplace_back(byteswap(word), vram);
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// If this is a branch or a direct jump, add it to the local label list
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if (instr.isBranch() || instr.getUniqueId() == rabbitizer::InstrId::UniqueId::cpu_j) {
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branch_labels.insert((uint32_t)instr.getBranchVramGeneric());
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}
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// Advance the vram address by the size of one instruction
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vram += 4;
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}
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// Analyze function
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RecompPort::FunctionStats stats{};
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if (!RecompPort::analyze_function(context, func, instructions, stats)) {
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fmt::print(stderr, "Failed to analyze {}\n", func.name);
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output_file.clear();
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return false;
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}
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std::unordered_set<uint32_t> skipped_insns{};
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// Add jump table labels into function
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for (const auto& jtbl : stats.jump_tables) {
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skipped_insns.insert(jtbl.lw_vram);
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for (uint32_t jtbl_entry : jtbl.entries) {
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branch_labels.insert(jtbl_entry);
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}
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}
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// Second pass, emit code for each instruction and emit labels
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auto cur_label = branch_labels.cbegin();
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vram = func.vram;
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int num_link_branches = 0;
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int num_likely_branches = 0;
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bool needs_link_branch = false;
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bool in_likely_delay_slot = false;
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const auto& section = context.sections[func.section_index];
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bool needs_reloc = section.relocatable;
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size_t reloc_index = 0;
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for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
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bool had_link_branch = needs_link_branch;
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bool is_branch_likely = false;
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// If we're in the delay slot of a likely instruction, emit a goto to skip the instruction before any labels
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if (in_likely_delay_slot) {
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fmt::print(output_file, " goto skip_{};\n", num_likely_branches);
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}
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// If there are any other branch labels to insert and we're at the next one, insert it
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if (cur_label != branch_labels.end() && vram >= *cur_label) {
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fmt::print(output_file, "L_{:08X}:\n", *cur_label);
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++cur_label;
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}
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// If this is a relocatable section, advance the reloc index until we reach the last one or until we get to/pass the current instruction
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if (needs_reloc) {
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while (reloc_index < (section.relocs.size() - 1) && section.relocs[reloc_index].address < vram) {
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reloc_index++;
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// If this is a branch or a direct jump, add it to the local label list
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if (instr.isBranch() || instr.getUniqueId() == rabbitizer::InstrId::UniqueId::cpu_j) {
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branch_labels.insert((uint32_t)instr.getBranchVramGeneric());
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}
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// Advance the vram address by the size of one instruction
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vram += 4;
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}
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// Process the current instruction and check for errors
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if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, reloc_index, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
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fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path.string() );
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// Analyze function
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RecompPort::FunctionStats stats{};
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if (!RecompPort::analyze_function(context, func, instructions, stats)) {
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fmt::print(stderr, "Failed to analyze {}\n", func.name);
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output_file.clear();
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return false;
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}
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// If a link return branch was generated, advance the number of link return branches
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if (had_link_branch) {
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num_link_branches++;
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std::unordered_set<uint32_t> skipped_insns{};
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// Add jump table labels into function
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for (const auto& jtbl : stats.jump_tables) {
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skipped_insns.insert(jtbl.lw_vram);
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for (uint32_t jtbl_entry : jtbl.entries) {
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branch_labels.insert(jtbl_entry);
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}
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}
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// Now that the instruction has been processed, emit a skip label for the likely branch if needed
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if (in_likely_delay_slot) {
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fmt::print(output_file, " skip_{}:\n", num_likely_branches);
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num_likely_branches++;
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// Second pass, emit code for each instruction and emit labels
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auto cur_label = branch_labels.cbegin();
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vram = func.vram;
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int num_link_branches = 0;
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int num_likely_branches = 0;
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bool needs_link_branch = false;
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bool in_likely_delay_slot = false;
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const auto& section = context.sections[func.section_index];
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bool needs_reloc = section.relocatable;
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size_t reloc_index = 0;
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for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
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bool had_link_branch = needs_link_branch;
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bool is_branch_likely = false;
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// If we're in the delay slot of a likely instruction, emit a goto to skip the instruction before any labels
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if (in_likely_delay_slot) {
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fmt::print(output_file, " goto skip_{};\n", num_likely_branches);
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}
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// If there are any other branch labels to insert and we're at the next one, insert it
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if (cur_label != branch_labels.end() && vram >= *cur_label) {
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fmt::print(output_file, "L_{:08X}:\n", *cur_label);
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++cur_label;
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}
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// If this is a relocatable section, advance the reloc index until we reach the last one or until we get to/pass the current instruction
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if (needs_reloc) {
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while (reloc_index < (section.relocs.size() - 1) && section.relocs[reloc_index].address < vram) {
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reloc_index++;
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}
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}
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// Process the current instruction and check for errors
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if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, reloc_index, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
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fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path.string());
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output_file.clear();
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return false;
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}
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// If a link return branch was generated, advance the number of link return branches
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if (had_link_branch) {
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num_link_branches++;
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}
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// Now that the instruction has been processed, emit a skip label for the likely branch if needed
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if (in_likely_delay_slot) {
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fmt::print(output_file, " skip_{}:\n", num_likely_branches);
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num_likely_branches++;
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}
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// Mark the next instruction as being in a likely delay slot if the
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in_likely_delay_slot = is_branch_likely;
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// Advance the vram address by the size of one instruction
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vram += 4;
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}
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// Mark the next instruction as being in a likely delay slot if the
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in_likely_delay_slot = is_branch_likely;
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// Advance the vram address by the size of one instruction
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vram += 4;
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}
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// Terminate the function
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