mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-30 23:33:15 +00:00
Implemented initial set of instructions and ignored functions
This commit is contained in:
Mr-Wiseguy
parent
4b1dc14019
commit
8a0f0da0cc
9 changed files with 1204 additions and 15 deletions
327
src/main.cpp
327
src/main.cpp
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@ -1,17 +1,330 @@
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#include <cstdio>
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#include <cstdlib>
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#include <unordered_set>
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#include <span>
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#include "rabbitizer.hpp"
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#include "elfio/elfio.hpp"
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#include "fmt/format.h"
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#include <cstdio>
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#include "recomp_port.h"
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std::unordered_set<std::string> ignored_funcs {
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// OS initialize functions
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"__createSpeedParam",
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"__osInitialize_common",
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"__osInitialize_autodetect",
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"osInitialize",
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// Audio interface functions
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"osAiGetLength",
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"osAiGetStatus",
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"osAiSetFrequency",
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"osAiSetNextBuffer",
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"__osAiDeviceBusy",
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// Video interface functions
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"osViBlack",
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"osViFade",
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"osViGetCurrentField",
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"osViGetCurrentFramebuffer",
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"osViGetCurrentLine",
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"osViGetCurrentMode",
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"osViGetNextFramebuffer",
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"osViGetStatus",
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"osViRepeatLine",
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"osViSetEvent",
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"osViSetMode",
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"osViSetSpecialFeatures",
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"osViSetXScale",
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"osViSetYScale",
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"osViSwapBuffer",
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"osCreateViManager",
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"viMgrMain",
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"__osViInit",
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"__osViSwapContext",
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"__osViGetCurrentContext",
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// RDP functions
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"osDpGetCounters",
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"osDpSetStatus",
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"osDpGetStatus",
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"osDpSetNextBuffer",
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"__osDpDeviceBusy",
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// RSP functions
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"osSpTaskLoad",
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"osSpTaskStartGo",
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"osSpTaskYield",
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"osSpTaskYielded",
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"__osSpDeviceBusy",
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"__osSpGetStatus",
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"__osSpRawStartDma",
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"__osSpRawReadIo",
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"__osSpRawWriteIo",
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"__osSpSetPc",
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"__osSpSetStatus",
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// Controller functions
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"osContGetQuery",
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"osContGetReadData",
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"osContInit",
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"osContReset",
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"osContSetCh",
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"osContStartQuery",
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"osContStartReadData",
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"__osContAddressCrc",
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"__osContDataCrc",
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"__osContGetInitData",
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"__osContRamRead",
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"__osContRamWrite",
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// EEPROM functions
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"osEepromLongRead",
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"osEepromLongWrite",
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"osEepromProbe",
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"osEepromRead",
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"osEepromWrite",
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"__osEepStatus",
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// Rumble functions
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"osMotorInit",
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"osMotorStart",
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"osMotorStop",
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// PFS functions
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"osPfsAllocateFile",
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"osPfsChecker",
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"osPfsDeleteFile",
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"osPfsFileState",
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"osPfsFindFile",
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"osPfsFreeBlocks",
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"osPfsGetLabel",
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"osPfsInit",
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"osPfsInitPak",
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"osPfsIsPlug",
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"osPfsNumFiles",
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"osPfsRepairId",
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"osPfsReadWriteFile",
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"__osPackEepReadData",
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"__osPackEepWriteData",
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"__osPackRamReadData",
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"__osPackRamWriteData",
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"__osPackReadData",
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"__osPackRequestData",
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"__osPfsGetInitData",
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"__osPfsGetOneChannelData",
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"__osPfsGetStatus",
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"__osPfsRequestData",
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"__osPfsRequestOneChannel",
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"__osPfsCreateAccessQueue",
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// Low level serial interface functions
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"__osSiDeviceBusy",
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"__osSiGetStatus",
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"__osSiRawStartDma",
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"__osSiRawReadIo",
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"__osSiRawWriteIo",
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"__osSiCreateAccessQueue",
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"__osSiGetAccess",
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"__osSiRelAccess",
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// Parallel interface (cartridge, DMA, etc.) functions
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"osCartRomInit",
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"osLeoDiskInit",
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"osCreatePiManager",
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"__osDevMgrMain",
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"osPiGetCmdQueue",
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"osPiGetStatus",
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"osPiReadIo",
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"osPiStartDma",
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"osPiWriteIo",
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"osEPiGetDeviceType",
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"osEPiStartDma",
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"osEPiWriteIo",
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"osEPiReadIo",
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"osPiRawStartDma",
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"osPiRawReadIo",
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"osPiRawWriteIo",
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"osEPiRawStartDma",
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"osEPiRawReadIo",
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"osEPiRawWriteIo",
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"__osPiRawStartDma",
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"__osPiRawReadIo",
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"__osPiRawWriteIo",
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"__osEPiRawStartDma",
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"__osEPiRawReadIo",
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"__osEPiRawWriteIo",
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"__osPiDeviceBusy",
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"__osPiCreateAccessQueue",
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"__osPiGetAccess",
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"__osPiRelAccess",
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"__osLeoAbnormalResume",
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"__osLeoInterrupt",
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"__osLeoResume",
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// Threading functions
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"osCreateThread",
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"osStartThread",
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"osStopThread",
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"osDestroyThread",
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"osYieldThread",
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"osSetThreadPri",
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"osGetThreadPri",
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"osGetThreadId",
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"__osDequeueThread",
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// Message Queue functions
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"osCreateMesgQueue",
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"osSendMesg",
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"osJamMesg",
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"osRecvMesg",
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"osSetEventMesg",
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// Timer functions
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"osStartTimer",
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"osSetTimer",
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"osStopTimer",
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"__osInsertTimer",
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"__osTimerInterrupt",
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"__osTimerServicesInit",
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"__osSetTimerIntr",
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// exceptasm functions
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"__osExceptionPreamble",
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"__osException",
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"send_mesg",
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"handle_CpU",
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"__osEnqueueAndYield",
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"__osEnqueueThread",
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"__osPopThread",
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"__osNop",
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"__osDispatchThread",
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"__osCleanupThread",
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"osGetCurrFaultedThread",
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"osGetNextFaultedThread",
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// interrupt functions
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"osSetIntMask",
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"osGetIntMask",
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"__osDisableInt",
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"__osRestoreInt",
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"__osSetGlobalIntMask",
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"__osResetGlobalIntMask",
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// TLB functions
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"osMapTLB",
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"osUnmapTLB",
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"osUnmapTLBAll",
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"osSetTLBASID",
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"osMapTLBRdb",
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"osVirtualToPhysical",
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"__osGetTLBHi",
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"__osGetTLBLo0",
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"__osGetTLBLo1",
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"__osGetTLBPageMask",
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"__osGetTLBASID",
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"__osProbeTLB",
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// Coprocessor 0 functions
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"__osSetCount",
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"osGetCount",
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"__osSetSR",
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"__osGetSR",
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"__osSetCause",
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"__osGetCause",
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"__osSetCompare",
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"__osGetCompare",
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"__osSetConfig",
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"__osGetConfig",
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"__osSetWatchLo",
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"__osGetWatchLo",
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};
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int main(int argc, char** argv) {
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uint32_t word = 0x8D4A7E18; // lw
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uint32_t vram = 0x80000000;
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int extraLJust = 5;
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rabbitizer::InstructionCpu instr(word, vram);
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if (argc != 2) {
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fmt::print("Usage: {} [input elf file]\n", argv[0]);
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std::exit(EXIT_SUCCESS);
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}
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fmt::print("{}\n", instr.isBranch());
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fmt::print("{:08X}: {}\n", word, instr.disassemble(extraLJust));
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ELFIO::elfio elf_file;
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auto exit_failure = [] (const std::string& error_str) {
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fmt::print(stderr, error_str);
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std::exit(EXIT_FAILURE);
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};
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if (!elf_file.load(argv[1])) {
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exit_failure("Failed to load provided elf file\n");
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}
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if (elf_file.get_class() != ELFIO::ELFCLASS32) {
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exit_failure("Incorrect elf class\n");
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}
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if (elf_file.get_encoding() != ELFIO::ELFDATA2MSB) {
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exit_failure("Incorrect endianness\n");
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}
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// Pointer to the symbol table section
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ELFIO::section* symtab_section = nullptr;
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// Size of the ROM as determined by the elf
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ELFIO::Elf_Xword rom_size = 0;
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// ROM address of each section
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std::vector<ELFIO::Elf_Xword> section_rom_addrs{};
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section_rom_addrs.resize(elf_file.sections.size());
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// Iterate over every section to record rom addresses and find the symbol table
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fmt::print("Sections\n");
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for (const std::unique_ptr<ELFIO::section>& section : elf_file.sections) {
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fmt::print(" {}: {} @ 0x{:08X}, 0x{:08X}\n", section->get_index(), section->get_name(), section->get_address(), rom_size);
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// Set the rom address of this section to the current accumulated ROM size
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section_rom_addrs[section->get_index()] = rom_size;
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// If this section isn't bss (SHT_NOBITS) and ends up in the rom (SHF_ALLOC), increase the rom size by this section's size
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if (section->get_type() != ELFIO::SHT_NOBITS && section->get_flags() & ELFIO::SHF_ALLOC) {
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rom_size += section->get_size();
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}
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// Check if this section is the symbol table and record it if so
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if (section->get_type() == ELFIO::SHT_SYMTAB) {
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symtab_section = section.get();
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}
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}
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// If no symbol table was found then exit
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if (symtab_section == nullptr) {
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exit_failure("No symbol section found\n");
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}
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ELFIO::symbol_section_accessor symbols{ elf_file, symtab_section };
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fmt::print("Num symbols: {}\n", symbols.get_symbols_num());
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std::vector<RecompPort::Function> functions{};
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functions.reserve(1024);
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for (int sym_index = 0; sym_index < symbols.get_symbols_num(); sym_index++) {
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std::string name;
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ELFIO::Elf64_Addr value;
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ELFIO::Elf_Xword size;
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unsigned char bind;
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unsigned char type;
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ELFIO::Elf_Half section_index;
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unsigned char other;
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// Read symbol properties
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symbols.get_symbol(sym_index, name, value, size, bind, type,
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section_index, other);
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// Check if this symbol is a function
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if (type == ELFIO::STT_FUNC) {
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auto section_rom_addr = section_rom_addrs[section_index];
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auto section_offset = value - elf_file.sections[section_index]->get_address();
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const uint32_t* words = reinterpret_cast<const uint32_t*>(elf_file.sections[section_index]->get_data() + section_offset);
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functions.emplace_back(
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static_cast<uint32_t>(value),
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static_cast<uint32_t>(section_offset + section_rom_addr),
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std::span{ reinterpret_cast<const uint32_t*>(words), size / 4 },
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std::move(name)
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);
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}
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}
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fmt::print("Function count: {}\n", functions.size());
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//#pragma omp parallel for
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for (size_t i = 0; i < functions.size(); i++) {
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const auto& func = functions[i];
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if (!ignored_funcs.contains(func.name)) {
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if (RecompPort::recompile_function(func, "out/" + func.name + ".c") == false) {
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fmt::print(stderr, "Error recompiling {}\n", func.name);
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std::exit(EXIT_FAILURE);
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}
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}
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}
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//RecompPort::recompile_function(functions.back(), "test.c");
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return 0;
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}
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719
src/recompilation.cpp
Normal file
719
src/recompilation.cpp
Normal file
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@ -0,0 +1,719 @@
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#include <vector>
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#include <set>
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#include "rabbitizer.hpp"
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#include "fmt/format.h"
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#include "fmt/ostream.h"
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#include "recomp_port.h"
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using InstrId = rabbitizer::InstrId::UniqueId;
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std::string_view ctx_gpr_prefix(int reg) {
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if (reg != 0) {
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return "ctx->r";
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}
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return "";
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}
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bool process_instruction(size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely) {
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const auto& instr = instructions[instr_index];
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needs_link_branch = false;
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is_branch_likely = false;
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// Output a comment with the original instruction
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if (instr.isBranch() || instr.getUniqueId() == InstrId::cpu_j) {
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fmt::print(output_file, " // {}\n", instr.disassemble(0, fmt::format("L_{:08X}", (uint32_t)instr.getBranchVramGeneric())));
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} else if (instr.getUniqueId() == InstrId::cpu_jal) {
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fmt::print(output_file, " // {}\n", instr.disassemble(0, "func"));
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} else {
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fmt::print(output_file, " // {}\n", instr.disassemble(0));
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}
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auto print_indent = [&]() {
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fmt::print(output_file, " ");
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};
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auto print_line = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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print_indent();
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fmt::print(output_file, fmt_str, args...);
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fmt::print(output_file, ";\n");
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};
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auto print_branch_condition = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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fmt::print(output_file, fmt_str, args...);
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fmt::print(output_file, " ");
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};
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auto print_branch = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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fmt::print(output_file, "{{\n ");
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if (instr_index < instructions.size() - 1) {
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bool dummy_needs_link_branch;
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bool dummy_is_branch_likely;
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process_instruction(instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
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}
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fmt::print(output_file, " ");
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fmt::print(output_file, fmt_str, args...);
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if (needs_link_branch) {
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fmt::print(output_file, ";\n goto after_{}", link_branch_index);
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}
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fmt::print(output_file, ";\n }}\n");
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};
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if (indent) {
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print_indent();
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}
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int rd = (int)instr.GetO32_rd();
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int rs = (int)instr.GetO32_rs();
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int base = rs;
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int rt = (int)instr.GetO32_rt();
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int sa = (int)instr.Get_sa();
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int fd = (int)instr.GetO32_fd();
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int fs = (int)instr.GetO32_fs();
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int ft = (int)instr.GetO32_ft();
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uint16_t imm = instr.Get_immediate();
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switch (instr.getUniqueId()) {
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case InstrId::cpu_nop:
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fmt::print(output_file, "\n");
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break;
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// Arithmetic
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case InstrId::cpu_lui:
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print_line("{}{} = {:#X} << 16", ctx_gpr_prefix(rt), rt, imm);
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break;
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case InstrId::cpu_addu:
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print_line("{}{} = ADD32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_negu: // pseudo instruction for subu x, 0, y
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case InstrId::cpu_subu:
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print_line("{}{} = SUB32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_addiu:
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print_line("{}{} = ADD32({}{}, {:#X})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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break;
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case InstrId::cpu_and:
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print_line("{}{} = {}{} & {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_andi:
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print_line("{}{} = {}{} & {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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break;
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case InstrId::cpu_or:
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print_line("{}{} = {}{} | {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_ori:
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print_line("{}{} = {}{} | {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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break;
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case InstrId::cpu_nor:
|
||||
print_line("{}{} = ~({}{} | {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_xor:
|
||||
print_line("{}{} = {}{} ^ {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_xori:
|
||||
print_line("{}{} = {}{} ^ {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
|
||||
break;
|
||||
case InstrId::cpu_sll:
|
||||
print_line("{}{} = S32({}{}) << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_sllv:
|
||||
print_line("{}{} = S32({}{}) << ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_sra:
|
||||
print_line("{}{} = S32(S64({}{}) >> {})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_srav:
|
||||
print_line("{}{} = S32(S64({}{}) >> ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_srl:
|
||||
print_line("{}{} = S32(U32({}{}) >> {})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_srlv:
|
||||
print_line("{}{} = S32(U32({}{}) >> ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_slt:
|
||||
print_line("{}{} = S64({}{}) < S64({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_slti:
|
||||
print_line("{}{} = S64({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
|
||||
break;
|
||||
case InstrId::cpu_sltu:
|
||||
print_line("{}{} = U64({}{}) < U64({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sltiu:
|
||||
print_line("{}{} = U64({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
|
||||
break;
|
||||
case InstrId::cpu_mult:
|
||||
print_line("uint64_t result = S64({}{}) * S64({}{}); lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_multu:
|
||||
print_line("uint64_t result = {}{} * {}{}; lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_div:
|
||||
print_line("lo = S32(S64({}{}) / S64({}{})); hi = S32(S64({}{}) % S64({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_divu:
|
||||
print_line("lo = S32(U32({}{}) / U32({}{})); hi = S32(U32({}{}) % U32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_mflo:
|
||||
print_line("{}{} = lo", ctx_gpr_prefix(rd), rd);
|
||||
break;
|
||||
case InstrId::cpu_mfhi:
|
||||
print_line("{}{} = hi", ctx_gpr_prefix(rd), rd);
|
||||
break;
|
||||
// Loads
|
||||
// TODO ld
|
||||
case InstrId::cpu_lw:
|
||||
print_line("{}{} = MEM_W({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lh:
|
||||
print_line("{}{} = MEM_H({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lb:
|
||||
print_line("{}{} = MEM_B({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lhu:
|
||||
print_line("{}{} = MEM_HU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lbu:
|
||||
print_line("{}{} = MEM_BU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
// Stores
|
||||
case InstrId::cpu_sw:
|
||||
print_line("MEM_W({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sh:
|
||||
print_line("MEM_H({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sb:
|
||||
print_line("MEM_B({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
// TODO lwl, lwr
|
||||
// examples:
|
||||
// reg = 11111111 01234567
|
||||
// mem @ x = 89ABCDEF
|
||||
|
||||
// LWL x + 0 -> FFFFFFFF 89ABCDEF
|
||||
// LWL x + 1 -> FFFFFFFF ABCDEF67
|
||||
// LWL x + 2 -> FFFFFFFF CDEF4567
|
||||
// LWL x + 3 -> FFFFFFFF EF234567
|
||||
|
||||
// LWR x + 0 -> 00000000 01234589
|
||||
// LWR x + 1 -> 00000000 012389AB
|
||||
// LWR x + 2 -> 00000000 0189ABCD
|
||||
// LWR x + 3 -> FFFFFFFF 89ABCDEF
|
||||
case InstrId::cpu_lwl:
|
||||
print_line("{}{} = MEM_WL({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lwr:
|
||||
print_line("{}{} = MEM_WR({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_swl:
|
||||
print_line("MEM_WL({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_swr:
|
||||
print_line("MEM_WR({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
|
||||
// Branches
|
||||
case InstrId::cpu_jal:
|
||||
needs_link_branch = true;
|
||||
print_indent();
|
||||
// TODO lookup function name
|
||||
print_branch("{}(rdram, ctx)", "func");
|
||||
break;
|
||||
case InstrId::cpu_jalr:
|
||||
needs_link_branch = true;
|
||||
print_indent();
|
||||
// TODO index global function table
|
||||
print_branch("{}(rdram, ctx)", "func_reg");
|
||||
break;
|
||||
case InstrId::cpu_j:
|
||||
case InstrId::cpu_b:
|
||||
print_indent();
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_jr:
|
||||
print_indent();
|
||||
if (rs == (int)rabbitizer::Registers::Cpu::GprO32::GPR_O32_ra) {
|
||||
print_branch("return");
|
||||
} else {
|
||||
// TODO jump table handling
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_bnel:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bne:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) != S32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_beql:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_beq:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) == S32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bnez:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) != 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_beqz:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) == 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bgezl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bgez:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) >= 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bgtzl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bgtz:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) > 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_blezl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_blez:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) <= 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bltzl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bltz:
|
||||
print_indent();
|
||||
print_branch_condition("if (S32({}{}) < 0)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_break:
|
||||
print_line("do_break();");
|
||||
break;
|
||||
|
||||
// Cop1 loads/stores
|
||||
case InstrId::cpu_mtc1:
|
||||
if ((fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = {}{}", fs, ctx_gpr_prefix(rt), rt);
|
||||
}
|
||||
else {
|
||||
// odd fpr
|
||||
print_line("ctx->f{}.u32h = {}{}", fs - 1, ctx_gpr_prefix(rt), rt);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mfc1:
|
||||
if ((fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("{}{} = ctx->f{}.u32l", ctx_gpr_prefix(rt), rt, fs);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("{}{} = ctx->f{}.u32h", ctx_gpr_prefix(rt), rt, fs - 1);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_lwc1:
|
||||
if ((ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = MEM_W({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("ctx->f{}.u32h = MEM_W({:#X}, {}{})", ft - 1, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_ldc1:
|
||||
if ((ft & 1) == 0) {
|
||||
print_line("ctx->f{}.u64 = MEM_D({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for ldc1: f{}\n", ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_swc1:
|
||||
if ((ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32l", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32h", (int16_t)imm, ctx_gpr_prefix(base), base, ft - 1);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sdc1:
|
||||
if ((ft & 1) == 0) {
|
||||
print_line("MEM_D({:#X}, {}{}) = ctx->f{}.u64", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for sdc1: f{}\n", ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
// Cop1 compares
|
||||
case InstrId::cpu_c_lt_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.lt.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_lt_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.lt.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_le_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.le.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_le_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.le.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_eq_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.eq.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_eq_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.eq.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
// Cop1 branches
|
||||
case InstrId::cpu_bc1tl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bc1t:
|
||||
print_indent();
|
||||
print_branch_condition("if (c1cs)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bc1fl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bc1f:
|
||||
print_indent();
|
||||
print_branch_condition("if (!c1cs)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
|
||||
// Cop1 arithmetic
|
||||
case InstrId::cpu_mov_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mov.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mov_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mov.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_neg_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = -ctx->f{}.fl", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for neg.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_neg_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = -ctx->f{}.d", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for neg.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_abs_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = fabsf(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for abs.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_abs_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = fabs(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for abs.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sqrt_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = sqrtf(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sqrt.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sqrt_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = sqrt(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sqrt.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_add_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl + ctx->f{}.fl", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for add.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_add_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d + ctx->f{}.d", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for add.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sub_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl - ctx->f{}.fl", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sub.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sub_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d - ctx->f{}.d", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sub.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mul_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = MUL_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mul.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mul_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = MUL_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mul.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_div_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = DIV_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for div.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_div_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = DIV_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for div.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_s_w:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = CVT_S_W(ctx->f{}.u32l)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.s.w: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_d_w:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = CVT_D_W(ctx->f{}.u32l)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.d.w: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_d_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = CVT_D_S(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.d.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_s_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = CVT_S_D(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.s.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_trunc_w_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = TRUNC_W_S(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for trunc.w.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_trunc_w_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = TRUNC_W_D(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for trunc.w.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
fmt::print(stderr, "Unhandled instruction: {}\n", instr.getOpcodeName());
|
||||
return false;
|
||||
}
|
||||
|
||||
if (emit_link_branch) {
|
||||
fmt::print(output_file, " after_{}:\n", link_branch_index);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool RecompPort::recompile_function(const RecompPort::Function& func, std::string_view output_path) {
|
||||
fmt::print("Recompiling {}\n", func.name);
|
||||
std::vector<rabbitizer::InstructionCpu> instructions;
|
||||
|
||||
// Open the output file and write the file header
|
||||
std::ofstream output_file{ output_path.data() };
|
||||
fmt::print(output_file,
|
||||
"#include \"recomp.h\"\n"
|
||||
"\n"
|
||||
"void {}(uint8_t* restrict rdram, recomp_context* restrict ctx) {{\n"
|
||||
// these variables shouldn't need to be preserved across function boundaries, so make them local for more efficient output
|
||||
" uint64_t hi = 0, lo = 0;\n"
|
||||
" int c1cs = 0; \n", // cop1 conditional signal
|
||||
func.name);
|
||||
|
||||
// Use a set to sort and deduplicate labels
|
||||
std::set<uint32_t> branch_labels;
|
||||
instructions.reserve(func.words.size());
|
||||
|
||||
// First pass, disassemble each instruction and collect branch labels
|
||||
uint32_t vram = func.vram;
|
||||
for (uint32_t word : func.words) {
|
||||
const auto& instr = instructions.emplace_back(byteswap(word), vram);
|
||||
|
||||
// If this is a branch or a direct jump, add it to the local label list
|
||||
if (instr.isBranch() || instr.getUniqueId() == rabbitizer::InstrId::UniqueId::cpu_j) {
|
||||
branch_labels.insert((uint32_t)instr.getBranchVramGeneric());
|
||||
}
|
||||
|
||||
// Advance the vram address by the size of one instruction
|
||||
vram += 4;
|
||||
}
|
||||
|
||||
// Second pass, emit code for each instruction and emit labels
|
||||
auto cur_label = branch_labels.cbegin();
|
||||
vram = func.vram;
|
||||
int num_link_branches = 0;
|
||||
int num_likely_branches = 0;
|
||||
bool needs_link_branch = false;
|
||||
bool in_likely_delay_slot = false;
|
||||
for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
|
||||
bool had_link_branch = needs_link_branch;
|
||||
bool is_branch_likely = false;
|
||||
// If we're in the delay slot of a likely instruction, emit a goto to skip the instruction before any labels
|
||||
if (in_likely_delay_slot) {
|
||||
fmt::print(output_file, " goto skip_{};\n", num_likely_branches);
|
||||
}
|
||||
// If there are any other branch labels to insert and we're at the next one, insert it
|
||||
if (cur_label != branch_labels.end() && vram >= *cur_label) {
|
||||
fmt::print(output_file, "L_{:08X}:\n", *cur_label);
|
||||
++cur_label;
|
||||
}
|
||||
// Process the current instruction and check for errors
|
||||
if (process_instruction(instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely) == false) {
|
||||
fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path);
|
||||
output_file.clear();
|
||||
return false;
|
||||
}
|
||||
// If a link return branch was generated, advance the number of link return branches
|
||||
if (had_link_branch) {
|
||||
num_link_branches++;
|
||||
}
|
||||
// Now that the instruction has been processed, emit a skip label for the likely branch if needed
|
||||
if (in_likely_delay_slot) {
|
||||
fmt::print(output_file, " skip_{}:\n", num_likely_branches);
|
||||
num_likely_branches++;
|
||||
}
|
||||
// Mark the next instruction as being in a likely delay slot if the
|
||||
in_likely_delay_slot = is_branch_likely;
|
||||
// Advance the vram address by the size of one instruction
|
||||
vram += 4;
|
||||
}
|
||||
|
||||
// Terminate the function
|
||||
fmt::print(output_file, "}}\n");
|
||||
|
||||
return true;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue