mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-24 12:24:59 +00:00
Implemented initial set of instructions and ignored functions
This commit is contained in:
Mr-Wiseguy
parent
4b1dc14019
commit
8a0f0da0cc
9 changed files with 1204 additions and 15 deletions
719
src/recompilation.cpp
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719
src/recompilation.cpp
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#include <vector>
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#include <set>
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#include "rabbitizer.hpp"
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#include "fmt/format.h"
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#include "fmt/ostream.h"
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#include "recomp_port.h"
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using InstrId = rabbitizer::InstrId::UniqueId;
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std::string_view ctx_gpr_prefix(int reg) {
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if (reg != 0) {
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return "ctx->r";
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}
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return "";
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}
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bool process_instruction(size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely) {
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const auto& instr = instructions[instr_index];
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needs_link_branch = false;
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is_branch_likely = false;
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// Output a comment with the original instruction
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if (instr.isBranch() || instr.getUniqueId() == InstrId::cpu_j) {
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fmt::print(output_file, " // {}\n", instr.disassemble(0, fmt::format("L_{:08X}", (uint32_t)instr.getBranchVramGeneric())));
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} else if (instr.getUniqueId() == InstrId::cpu_jal) {
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fmt::print(output_file, " // {}\n", instr.disassemble(0, "func"));
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} else {
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fmt::print(output_file, " // {}\n", instr.disassemble(0));
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}
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auto print_indent = [&]() {
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fmt::print(output_file, " ");
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};
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auto print_line = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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print_indent();
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fmt::print(output_file, fmt_str, args...);
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fmt::print(output_file, ";\n");
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};
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auto print_branch_condition = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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fmt::print(output_file, fmt_str, args...);
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fmt::print(output_file, " ");
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};
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auto print_branch = [&]<typename... Ts>(fmt::format_string<Ts...> fmt_str, Ts ...args) {
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fmt::print(output_file, "{{\n ");
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if (instr_index < instructions.size() - 1) {
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bool dummy_needs_link_branch;
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bool dummy_is_branch_likely;
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process_instruction(instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
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}
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fmt::print(output_file, " ");
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fmt::print(output_file, fmt_str, args...);
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if (needs_link_branch) {
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fmt::print(output_file, ";\n goto after_{}", link_branch_index);
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}
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fmt::print(output_file, ";\n }}\n");
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};
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if (indent) {
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print_indent();
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}
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int rd = (int)instr.GetO32_rd();
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int rs = (int)instr.GetO32_rs();
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int base = rs;
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int rt = (int)instr.GetO32_rt();
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int sa = (int)instr.Get_sa();
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int fd = (int)instr.GetO32_fd();
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int fs = (int)instr.GetO32_fs();
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int ft = (int)instr.GetO32_ft();
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uint16_t imm = instr.Get_immediate();
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switch (instr.getUniqueId()) {
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case InstrId::cpu_nop:
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fmt::print(output_file, "\n");
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break;
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// Arithmetic
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case InstrId::cpu_lui:
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print_line("{}{} = {:#X} << 16", ctx_gpr_prefix(rt), rt, imm);
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break;
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case InstrId::cpu_addu:
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print_line("{}{} = ADD32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_negu: // pseudo instruction for subu x, 0, y
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case InstrId::cpu_subu:
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print_line("{}{} = SUB32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_addiu:
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print_line("{}{} = ADD32({}{}, {:#X})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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break;
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case InstrId::cpu_and:
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print_line("{}{} = {}{} & {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_andi:
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print_line("{}{} = {}{} & {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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break;
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case InstrId::cpu_or:
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print_line("{}{} = {}{} | {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_ori:
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print_line("{}{} = {}{} | {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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break;
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case InstrId::cpu_nor:
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print_line("{}{} = ~({}{} | {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_xor:
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print_line("{}{} = {}{} ^ {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_xori:
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print_line("{}{} = {}{} ^ {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
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break;
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case InstrId::cpu_sll:
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print_line("{}{} = S32({}{}) << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
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break;
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case InstrId::cpu_sllv:
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print_line("{}{} = S32({}{}) << ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
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break;
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case InstrId::cpu_sra:
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print_line("{}{} = S32(S64({}{}) >> {})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
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break;
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case InstrId::cpu_srav:
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print_line("{}{} = S32(S64({}{}) >> ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
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break;
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case InstrId::cpu_srl:
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print_line("{}{} = S32(U32({}{}) >> {})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
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break;
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case InstrId::cpu_srlv:
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print_line("{}{} = S32(U32({}{}) >> ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
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break;
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case InstrId::cpu_slt:
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print_line("{}{} = S64({}{}) < S64({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_slti:
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print_line("{}{} = S64({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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break;
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case InstrId::cpu_sltu:
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print_line("{}{} = U64({}{}) < U64({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sltiu:
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print_line("{}{} = U64({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
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break;
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case InstrId::cpu_mult:
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print_line("uint64_t result = S64({}{}) * S64({}{}); lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_multu:
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print_line("uint64_t result = {}{} * {}{}; lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_div:
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print_line("lo = S32(S64({}{}) / S64({}{})); hi = S32(S64({}{}) % S64({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_divu:
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print_line("lo = S32(U32({}{}) / U32({}{})); hi = S32(U32({}{}) % U32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_mflo:
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print_line("{}{} = lo", ctx_gpr_prefix(rd), rd);
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break;
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case InstrId::cpu_mfhi:
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print_line("{}{} = hi", ctx_gpr_prefix(rd), rd);
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break;
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// Loads
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// TODO ld
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case InstrId::cpu_lw:
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print_line("{}{} = MEM_W({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lh:
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print_line("{}{} = MEM_H({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lb:
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print_line("{}{} = MEM_B({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lhu:
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print_line("{}{} = MEM_HU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lbu:
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print_line("{}{} = MEM_BU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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// Stores
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case InstrId::cpu_sw:
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print_line("MEM_W({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sh:
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print_line("MEM_H({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_sb:
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print_line("MEM_B({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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// TODO lwl, lwr
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// examples:
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// reg = 11111111 01234567
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// mem @ x = 89ABCDEF
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// LWL x + 0 -> FFFFFFFF 89ABCDEF
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// LWL x + 1 -> FFFFFFFF ABCDEF67
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// LWL x + 2 -> FFFFFFFF CDEF4567
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// LWL x + 3 -> FFFFFFFF EF234567
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// LWR x + 0 -> 00000000 01234589
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// LWR x + 1 -> 00000000 012389AB
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// LWR x + 2 -> 00000000 0189ABCD
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// LWR x + 3 -> FFFFFFFF 89ABCDEF
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case InstrId::cpu_lwl:
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print_line("{}{} = MEM_WL({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_lwr:
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print_line("{}{} = MEM_WR({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_swl:
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print_line("MEM_WL({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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case InstrId::cpu_swr:
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print_line("MEM_WR({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
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break;
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// Branches
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case InstrId::cpu_jal:
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needs_link_branch = true;
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print_indent();
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// TODO lookup function name
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print_branch("{}(rdram, ctx)", "func");
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break;
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case InstrId::cpu_jalr:
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needs_link_branch = true;
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print_indent();
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// TODO index global function table
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print_branch("{}(rdram, ctx)", "func_reg");
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break;
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case InstrId::cpu_j:
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case InstrId::cpu_b:
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print_indent();
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_jr:
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print_indent();
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if (rs == (int)rabbitizer::Registers::Cpu::GprO32::GPR_O32_ra) {
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print_branch("return");
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} else {
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// TODO jump table handling
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}
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break;
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case InstrId::cpu_bnel:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_bne:
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print_indent();
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print_branch_condition("if (S32({}{}) != S32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_beql:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_beq:
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print_indent();
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print_branch_condition("if (S32({}{}) == S32({}{}))", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_bnez:
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print_indent();
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print_branch_condition("if (S32({}{}) != 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_beqz:
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print_indent();
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print_branch_condition("if (S32({}{}) == 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_bgezl:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_bgez:
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print_indent();
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print_branch_condition("if (S32({}{}) >= 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_bgtzl:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_bgtz:
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print_indent();
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print_branch_condition("if (S32({}{}) > 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_blezl:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_blez:
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print_indent();
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print_branch_condition("if (S32({}{}) <= 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_bltzl:
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is_branch_likely = true;
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[[fallthrough]];
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case InstrId::cpu_bltz:
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print_indent();
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print_branch_condition("if (S32({}{}) < 0)", ctx_gpr_prefix(rs), rs);
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print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
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break;
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case InstrId::cpu_break:
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print_line("do_break();");
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break;
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// Cop1 loads/stores
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case InstrId::cpu_mtc1:
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if ((fs & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = {}{}", fs, ctx_gpr_prefix(rt), rt);
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}
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else {
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// odd fpr
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print_line("ctx->f{}.u32h = {}{}", fs - 1, ctx_gpr_prefix(rt), rt);
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}
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break;
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case InstrId::cpu_mfc1:
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if ((fs & 1) == 0) {
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// even fpr
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print_line("{}{} = ctx->f{}.u32l", ctx_gpr_prefix(rt), rt, fs);
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} else {
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// odd fpr
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print_line("{}{} = ctx->f{}.u32h", ctx_gpr_prefix(rt), rt, fs - 1);
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}
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break;
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case InstrId::cpu_lwc1:
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if ((ft & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = MEM_W({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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} else {
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// odd fpr
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print_line("ctx->f{}.u32h = MEM_W({:#X}, {}{})", ft - 1, (int16_t)imm, ctx_gpr_prefix(base), base);
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}
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break;
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case InstrId::cpu_ldc1:
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if ((ft & 1) == 0) {
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print_line("ctx->f{}.u64 = MEM_D({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
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} else {
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fmt::print(stderr, "Invalid operand for ldc1: f{}\n", ft);
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return false;
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}
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break;
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case InstrId::cpu_swc1:
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if ((ft & 1) == 0) {
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// even fpr
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print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32l", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
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} else {
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// odd fpr
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print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32h", (int16_t)imm, ctx_gpr_prefix(base), base, ft - 1);
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}
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break;
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case InstrId::cpu_sdc1:
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if ((ft & 1) == 0) {
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print_line("MEM_D({:#X}, {}{}) = ctx->f{}.u64", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
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} else {
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fmt::print(stderr, "Invalid operand for sdc1: f{}\n", ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
// Cop1 compares
|
||||
case InstrId::cpu_c_lt_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.lt.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_lt_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.lt.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_le_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.le.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_le_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.le.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_eq_s:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.eq.s: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_c_eq_d:
|
||||
if ((fs & 1) == 0 && (ft & 1) == 0) {
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for c.eq.d: f{} f{}\n", fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
// Cop1 branches
|
||||
case InstrId::cpu_bc1tl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bc1t:
|
||||
print_indent();
|
||||
print_branch_condition("if (c1cs)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
case InstrId::cpu_bc1fl:
|
||||
is_branch_likely = true;
|
||||
[[fallthrough]];
|
||||
case InstrId::cpu_bc1f:
|
||||
print_indent();
|
||||
print_branch_condition("if (!c1cs)", ctx_gpr_prefix(rs), rs);
|
||||
print_branch("goto L_{:08X}", (uint32_t)instr.getBranchVramGeneric());
|
||||
break;
|
||||
|
||||
// Cop1 arithmetic
|
||||
case InstrId::cpu_mov_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mov.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mov_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mov.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_neg_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = -ctx->f{}.fl", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for neg.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_neg_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = -ctx->f{}.d", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for neg.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_abs_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = fabsf(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for abs.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_abs_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = fabs(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for abs.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sqrt_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = sqrtf(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sqrt.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sqrt_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = sqrt(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sqrt.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_add_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl + ctx->f{}.fl", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for add.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_add_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d + ctx->f{}.d", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for add.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sub_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = ctx->f{}.fl - ctx->f{}.fl", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sub.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sub_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = ctx->f{}.d - ctx->f{}.d", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for sub.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mul_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = MUL_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mul.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_mul_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = MUL_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for mul.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_div_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = DIV_S(ctx->f{}.fl, ctx->f{}.fl)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for div.s: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_div_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0 && (ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = DIV_D(ctx->f{}.d, ctx->f{}.d)", fd, fs, ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for div.d: f{} f{} f{}\n", fd, fs, ft);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_s_w:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = CVT_S_W(ctx->f{}.u32l)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.s.w: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_d_w:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = CVT_D_W(ctx->f{}.u32l)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.d.w: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_d_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.d = CVT_D_S(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.d.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_cvt_s_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.fl = CVT_S_D(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for cvt.s.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_trunc_w_s:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = TRUNC_W_S(ctx->f{}.fl)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for trunc.w.s: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_trunc_w_d:
|
||||
if ((fd & 1) == 0 && (fs & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = TRUNC_W_D(ctx->f{}.d)", fd, fs);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand(s) for trunc.w.d: f{} f{}\n", fd, fs);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
fmt::print(stderr, "Unhandled instruction: {}\n", instr.getOpcodeName());
|
||||
return false;
|
||||
}
|
||||
|
||||
if (emit_link_branch) {
|
||||
fmt::print(output_file, " after_{}:\n", link_branch_index);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool RecompPort::recompile_function(const RecompPort::Function& func, std::string_view output_path) {
|
||||
fmt::print("Recompiling {}\n", func.name);
|
||||
std::vector<rabbitizer::InstructionCpu> instructions;
|
||||
|
||||
// Open the output file and write the file header
|
||||
std::ofstream output_file{ output_path.data() };
|
||||
fmt::print(output_file,
|
||||
"#include \"recomp.h\"\n"
|
||||
"\n"
|
||||
"void {}(uint8_t* restrict rdram, recomp_context* restrict ctx) {{\n"
|
||||
// these variables shouldn't need to be preserved across function boundaries, so make them local for more efficient output
|
||||
" uint64_t hi = 0, lo = 0;\n"
|
||||
" int c1cs = 0; \n", // cop1 conditional signal
|
||||
func.name);
|
||||
|
||||
// Use a set to sort and deduplicate labels
|
||||
std::set<uint32_t> branch_labels;
|
||||
instructions.reserve(func.words.size());
|
||||
|
||||
// First pass, disassemble each instruction and collect branch labels
|
||||
uint32_t vram = func.vram;
|
||||
for (uint32_t word : func.words) {
|
||||
const auto& instr = instructions.emplace_back(byteswap(word), vram);
|
||||
|
||||
// If this is a branch or a direct jump, add it to the local label list
|
||||
if (instr.isBranch() || instr.getUniqueId() == rabbitizer::InstrId::UniqueId::cpu_j) {
|
||||
branch_labels.insert((uint32_t)instr.getBranchVramGeneric());
|
||||
}
|
||||
|
||||
// Advance the vram address by the size of one instruction
|
||||
vram += 4;
|
||||
}
|
||||
|
||||
// Second pass, emit code for each instruction and emit labels
|
||||
auto cur_label = branch_labels.cbegin();
|
||||
vram = func.vram;
|
||||
int num_link_branches = 0;
|
||||
int num_likely_branches = 0;
|
||||
bool needs_link_branch = false;
|
||||
bool in_likely_delay_slot = false;
|
||||
for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
|
||||
bool had_link_branch = needs_link_branch;
|
||||
bool is_branch_likely = false;
|
||||
// If we're in the delay slot of a likely instruction, emit a goto to skip the instruction before any labels
|
||||
if (in_likely_delay_slot) {
|
||||
fmt::print(output_file, " goto skip_{};\n", num_likely_branches);
|
||||
}
|
||||
// If there are any other branch labels to insert and we're at the next one, insert it
|
||||
if (cur_label != branch_labels.end() && vram >= *cur_label) {
|
||||
fmt::print(output_file, "L_{:08X}:\n", *cur_label);
|
||||
++cur_label;
|
||||
}
|
||||
// Process the current instruction and check for errors
|
||||
if (process_instruction(instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely) == false) {
|
||||
fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path);
|
||||
output_file.clear();
|
||||
return false;
|
||||
}
|
||||
// If a link return branch was generated, advance the number of link return branches
|
||||
if (had_link_branch) {
|
||||
num_link_branches++;
|
||||
}
|
||||
// Now that the instruction has been processed, emit a skip label for the likely branch if needed
|
||||
if (in_likely_delay_slot) {
|
||||
fmt::print(output_file, " skip_{}:\n", num_likely_branches);
|
||||
num_likely_branches++;
|
||||
}
|
||||
// Mark the next instruction as being in a likely delay slot if the
|
||||
in_likely_delay_slot = is_branch_likely;
|
||||
// Advance the vram address by the size of one instruction
|
||||
vram += 4;
|
||||
}
|
||||
|
||||
// Terminate the function
|
||||
fmt::print(output_file, "}}\n");
|
||||
|
||||
return true;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue