mirror of
https://github.com/N64Recomp/N64Recomp.git
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Implement relocations in live recompiler
This commit is contained in:
Mr-Wiseguy
parent
9fa9adbe3a
commit
aa765c435f
4 changed files with 155 additions and 65 deletions
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@ -236,14 +236,10 @@ void get_gpr_values(int gpr, sljit_sw& out, sljit_sw& outw) {
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}
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}
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void get_operand_values(N64Recomp::Operand operand, const N64Recomp::InstructionContext& context, sljit_sw& out, sljit_sw& outw, bool& needs_relocation) {
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void get_operand_values(N64Recomp::Operand operand, const N64Recomp::InstructionContext& context, sljit_sw& out, sljit_sw& outw) {
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using namespace N64Recomp;
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bool relocation_valid = false;
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// Relocations are only valid for ImmS16 and ImmU16 operands.
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assert(context.reloc_type == RelocType::R_MIPS_NONE ||
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(operand == Operand::ImmS16 || operand == Operand::ImmU16));
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switch (operand) {
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case Operand::Rd:
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get_gpr_values(context.rd, out, outw);
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@ -312,12 +308,10 @@ void get_operand_values(N64Recomp::Operand operand, const N64Recomp::Instruction
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outw = get_fpr_u64_context_offset(context.ft);
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break;
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case Operand::ImmU16:
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relocation_valid = true;
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out = SLJIT_IMM;
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outw = (sljit_sw)(uint16_t)context.imm16;
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break;
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case Operand::ImmS16:
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relocation_valid = true;
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out = SLJIT_IMM;
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outw = (sljit_sw)(int16_t)context.imm16;
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break;
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@ -346,13 +340,6 @@ void get_operand_values(N64Recomp::Operand operand, const N64Recomp::Instruction
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outw = 0;
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break;
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}
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if (context.reloc_type != N64Recomp::RelocType::R_MIPS_NONE) {
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assert(relocation_valid && "Relocation present but not valid on the given operand!");
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needs_relocation = true;
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}
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else {
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needs_relocation = false;
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}
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}
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bool outputs_to_zero(N64Recomp::Operand output, const N64Recomp::InstructionContext& ctx) {
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@ -377,25 +364,48 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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bool failed = false;
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sljit_sw dst;
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sljit_sw dstw;
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bool relocation_needed_dst;
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sljit_sw src1;
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sljit_sw src1w;
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bool relocation_needed_src1;
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sljit_sw src2;
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sljit_sw src2w;
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bool relocation_needed_src2;
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get_operand_values(op.output, ctx, dst, dstw, relocation_needed_dst);
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get_operand_values(op.operands.operands[0], ctx, src1, src1w, relocation_needed_src1);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w, relocation_needed_src2);
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get_operand_values(op.output, ctx, dst, dstw);
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get_operand_values(op.operands.operands[0], ctx, src1, src1w);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w);
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// Relocations are only valid on the second operand.
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assert(!relocation_needed_dst && !relocation_needed_src1);
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// TODO perform relocation.
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// If a relocation is needed for the second operand, perform the relocation and change src2/src2w to use the relocated value.
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if (relocation_needed_src2) {
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// If a relocation is present, perform the relocation and change src1/src1w to use the relocated value.
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if (ctx.reloc_type != RelocType::R_MIPS_NONE) {
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// Only allow LO16 relocations.
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assert(ctx.reloc_type == RelocType::R_MIPS_LO16);
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// Only allow relocations on immediates.
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assert(src2 == SLJIT_IMM);
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// Only allow relocations on loads and adds.
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switch (op.type) {
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case BinaryOpType::LD:
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case BinaryOpType::LW:
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case BinaryOpType::LWU:
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case BinaryOpType::LH:
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case BinaryOpType::LHU:
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case BinaryOpType::LB:
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case BinaryOpType::LBU:
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case BinaryOpType::LDL:
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case BinaryOpType::LDR:
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case BinaryOpType::LWL:
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case BinaryOpType::LWR:
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case BinaryOpType::Add64:
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case BinaryOpType::Add32:
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break;
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default:
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// Relocations aren't allowed on this instruction.
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assert(false);
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}
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// Load the relocated address into temp2.
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load_relocated_address(ctx, Registers::arithmetic_temp1);
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// Extract the LO16 value from the full address (sign extended lower 16 bits).
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sljit_emit_op1(compiler, SLJIT_MOV_S16, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0);
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// Replace the immediate input (src2) with the LO16 value.
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src2 = Registers::arithmetic_temp1;
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src2w = 0;
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}
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// TODO validate that the unary ops are valid for the current binary op.
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assert(op.operands.operand_operations[0] == UnaryOpType::None ||
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@ -750,6 +760,20 @@ int64_t do_floor_l_d(double num) {
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return (int64_t)floor(num);
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}
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void N64Recomp::LiveGenerator::load_relocated_address(const InstructionContext& ctx, int reg) const {
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// Get the pointer to the section address.
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int32_t* section_addr_ptr = (ctx.reloc_tag_as_reference ? inputs.reference_section_addresses : inputs.local_section_addresses) + ctx.reloc_section_index;
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// Load the section's address into R0.
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sljit_emit_op1(compiler, SLJIT_MOV_S32, Registers::arithmetic_temp1, 0, SLJIT_MEM0(), sljit_sw(section_addr_ptr));
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// Don't emit the add if the offset is zero (small optimization).
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if (ctx.reloc_target_section_offset != 0) {
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// Add the reloc section offset to the section's address and put the result in R0.
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sljit_emit_op2(compiler, SLJIT_ADD, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0, SLJIT_IMM, ctx.reloc_target_section_offset);
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}
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}
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void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const InstructionContext& ctx) const {
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// Skip instructions that output to $zero
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if (outputs_to_zero(op.output, ctx)) {
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@ -758,20 +782,37 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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sljit_sw dst;
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sljit_sw dstw;
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bool relocation_needed_dst;
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sljit_sw src;
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sljit_sw srcw;
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bool relocation_needed_src;
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get_operand_values(op.output, ctx, dst, dstw, relocation_needed_dst);
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get_operand_values(op.input, ctx, src, srcw, relocation_needed_src);
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get_operand_values(op.output, ctx, dst, dstw);
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get_operand_values(op.input, ctx, src, srcw);
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// Relocations aren't valid on the output operand.
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assert(!relocation_needed_dst);
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// TODO perform relocation.
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// If a relocation is needed for the input operand, perform the relocation and change src/srcw to use the relocated value.
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if (relocation_needed_src) {
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// If a relocation is needed for the input operand, perform the relocation and store the result directly.
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if (ctx.reloc_type != RelocType::R_MIPS_NONE) {
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// Only allow relocation of lui with an immediate.
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if (op.operation != UnaryOpType::Lui || op.input != Operand::ImmU16) {
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assert(false);
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return;
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}
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// Only allow HI16 relocs.
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if (ctx.reloc_type != RelocType::R_MIPS_HI16) {
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assert(false);
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return;
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}
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// Load the relocated address into temp1.
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load_relocated_address(ctx, Registers::arithmetic_temp1);
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// HI16 reloc on a lui
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// The 32-bit address (a) is equal to section address + section offset
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// The 16-bit immediate is equal to (a - (int16_t)a) >> 16
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// Therefore, the register should be set to (int32_t)(a - (int16_t)a) as the shifts cancel out and the lower 16 bits are zero.
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// Extract a sign extended 16-bit value from the lower half of the relocated address and put it in temp2.
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sljit_emit_op1(compiler, SLJIT_MOV_S16, Registers::arithmetic_temp2, 0, Registers::arithmetic_temp1, 0);
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// Subtract the sign extended 16-bit value from the full address to get the HI16 value and place it in the destination.
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sljit_emit_op2(compiler, SLJIT_SUB, dst, dstw, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp2, 0);
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return;
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}
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sljit_s32 jit_op = SLJIT_BREAKPOINT;
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@ -986,16 +1027,25 @@ void N64Recomp::LiveGenerator::process_unary_op(const UnaryOp& op, const Instruc
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void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const InstructionContext& ctx) const {
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sljit_sw src;
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sljit_sw srcw;
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bool relocation_needed_src;
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sljit_sw imm = (sljit_sw)(int16_t)ctx.imm16;
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get_operand_values(op.value_input, ctx, src, srcw, relocation_needed_src);
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get_operand_values(op.value_input, ctx, src, srcw);
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// Relocations aren't valid on the input operand.
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assert(!relocation_needed_src);
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// Only LO16 relocs are valid on stores.
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assert(ctx.reloc_type == RelocType::R_MIPS_NONE || ctx.reloc_type == RelocType::R_MIPS_LO16);
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if (ctx.reloc_type == RelocType::R_MIPS_LO16) {
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// Load the relocated address into temp1.
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load_relocated_address(ctx, Registers::arithmetic_temp1);
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// Extract the LO16 value from the full address (sign extended lower 16 bits).
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sljit_emit_op1(compiler, SLJIT_MOV_S16, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0);
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// Add the base register (rs) to the LO16 immediate.
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sljit_emit_op2(compiler, SLJIT_ADD, Registers::arithmetic_temp1, 0, Registers::arithmetic_temp1, 0, SLJIT_MEM1(Registers::ctx), get_gpr_context_offset(ctx.rs));
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}
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else {
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// Add the base register (rs) and the immediate to get the address and store it in the arithemtic temp.
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sljit_emit_op2(compiler, SLJIT_ADD, Registers::arithmetic_temp1, 0, SLJIT_MEM1(Registers::ctx), get_gpr_context_offset(ctx.rs), SLJIT_IMM, imm);
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}
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switch (op.type) {
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case StoreOpType::SD:
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@ -1186,16 +1236,14 @@ void N64Recomp::LiveGenerator::emit_branch_condition(const ConditionalBranchOp&
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}
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sljit_sw src1;
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sljit_sw src1w;
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bool relocation_needed_src1;
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sljit_sw src2;
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sljit_sw src2w;
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bool relocation_needed_src2;
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get_operand_values(op.operands.operands[0], ctx, src1, src1w, relocation_needed_src1);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w, relocation_needed_src2);
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get_operand_values(op.operands.operands[0], ctx, src1, src1w);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w);
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// Relocations aren't valid on the input operands.
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assert(!relocation_needed_src1 && !relocation_needed_src2);
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// Relocations aren't valid on conditional branches.
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assert(ctx.reloc_type == RelocType::R_MIPS_NONE);
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// Create a compare jump and track it as the pending branch jump.
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context->cur_branch_jump = sljit_emit_cmp(compiler, condition_type, src1, src1w, src2, src2w);
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@ -115,17 +115,26 @@ TestStats run_test(const std::filesystem::path& tests_dir, const std::string& te
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// Move the file data into the context.
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context.rom = std::move(file_data);
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context.sections.resize(2);
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// Create a section for the function to exist in.
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context.sections.resize(1);
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context.sections[0].ram_addr = text_address;
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context.sections[0].rom_addr = text_offset;
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context.sections[0].size = text_length;
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context.sections[0].name = "test_section";
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context.sections[0].name = ".text";
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context.sections[0].executable = true;
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context.sections[0].relocatable = true;
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context.section_functions.resize(context.sections.size());
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// Create a section for .data (used for relocations)
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context.sections[1].ram_addr = data_address;
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context.sections[1].rom_addr = init_data_offset;
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context.sections[1].size = data_length;
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context.sections[1].name = ".data";
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context.sections[1].executable = false;
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context.sections[1].relocatable = true;
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size_t start_func_index;
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uint32_t function_desc_address = 0;
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uint32_t reloc_desc_address = 0;
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// Read any extra structs.
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while (next_struct_address != 0) {
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@ -137,6 +146,9 @@ TestStats run_test(const std::filesystem::path& tests_dir, const std::string& te
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case 1: // Function desc
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function_desc_address = cur_struct_address;
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break;
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case 2: // Relocation
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reloc_desc_address = cur_struct_address;
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break;
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default:
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printf("Unknown struct type %u\n", struct_type);
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return { TestError::UnknownStructType };
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@ -198,13 +210,39 @@ TestStats run_test(const std::filesystem::path& tests_dir, const std::string& te
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}
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}
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// Check if a relocation description exists.
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if (reloc_desc_address != 0) {
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uint32_t num_relocs = read_u32_swap(context.rom, reloc_desc_address + 0x08);
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for (uint32_t reloc_index = 0; reloc_index < num_relocs; reloc_index++) {
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uint32_t cur_desc_address = reloc_desc_address + 0x0C + reloc_index * 4 * sizeof(uint32_t);
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uint32_t reloc_type = read_u32_swap(context.rom, cur_desc_address + 0x00);
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uint32_t reloc_section = read_u32_swap(context.rom, cur_desc_address + 0x04);
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uint32_t reloc_address = read_u32_swap(context.rom, cur_desc_address + 0x08);
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uint32_t reloc_target_offset = read_u32_swap(context.rom, cur_desc_address + 0x0C);
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context.sections[0].relocs.emplace_back(N64Recomp::Reloc{
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.address = reloc_address,
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.target_section_offset = reloc_target_offset,
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.symbol_index = 0,
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.target_section = static_cast<uint16_t>(reloc_section),
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.type = static_cast<N64Recomp::RelocType>(reloc_type),
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.reference_symbol = false
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});
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}
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}
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std::vector<std::vector<uint32_t>> dummy_static_funcs{};
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std::vector<int32_t> section_addresses{};
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section_addresses.emplace_back(text_address);
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section_addresses.emplace_back(data_address);
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auto before_codegen = std::chrono::system_clock::now();
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N64Recomp::LiveGeneratorInputs generator_inputs {
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.switch_error = test_switch_error,
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.get_function = test_get_function,
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.reference_section_addresses = nullptr,
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.local_section_addresses = section_addresses.data()
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};
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// Create the sljit compiler and the generator.
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@ -54,6 +54,8 @@ namespace N64Recomp {
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void (*syscall_handler)(uint8_t* rdram, recomp_context* ctx, int32_t instruction_vram);
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void (*pause_self)(uint8_t* rdram);
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void (*trigger_event)(uint8_t* rdram, recomp_context* ctx, uint32_t event_index);
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int32_t *reference_section_addresses;
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int32_t *local_section_addresses;
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};
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class LiveGenerator final : public Generator {
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public:
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@ -101,6 +103,8 @@ namespace N64Recomp {
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void get_operand_string(Operand operand, UnaryOpType operation, const InstructionContext& context, std::string& operand_string) const;
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void get_binary_expr_string(BinaryOpType type, const BinaryOperands& operands, const InstructionContext& ctx, const std::string& output, std::string& expr_string) const;
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void get_notation(BinaryOpType op_type, std::string& func_string, std::string& infix_string) const;
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// Loads the relocated address specified by the instruction context into R0.
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void load_relocated_address(const InstructionContext& ctx, int reg) const;
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sljit_compiler* compiler;
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LiveGeneratorInputs inputs;
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mutable std::unique_ptr<LiveGeneratorContext> context;
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@ -127,19 +127,19 @@ namespace N64Recomp {
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/* TODO rename to c_seq_d when fixed in rabbitizer */
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{ InstrId::cpu_c_deq_d, { BinaryOpType::Equal, Operand::Cop1cs, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::FsDouble, Operand::FtDouble }}, true } },
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// Loads
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{ InstrId::cpu_ld, { BinaryOpType::LD, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lw, { BinaryOpType::LW, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwu, { BinaryOpType::LWU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lh, { BinaryOpType::LH, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lhu, { BinaryOpType::LHU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lb, { BinaryOpType::LB, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lbu, { BinaryOpType::LBU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldl, { BinaryOpType::LDL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldr, { BinaryOpType::LDR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwl, { BinaryOpType::LWL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwr, { BinaryOpType::LWR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwc1, { BinaryOpType::LW, Operand::FtU32L, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldc1, { BinaryOpType::LD, Operand::FtU64, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}, true } },
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{ InstrId::cpu_ld, { BinaryOpType::LD, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lw, { BinaryOpType::LW, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lwu, { BinaryOpType::LWU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lh, { BinaryOpType::LH, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lhu, { BinaryOpType::LHU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lb, { BinaryOpType::LB, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lbu, { BinaryOpType::LBU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_ldl, { BinaryOpType::LDL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_ldr, { BinaryOpType::LDR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lwl, { BinaryOpType::LWL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lwr, { BinaryOpType::LWR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_lwc1, { BinaryOpType::LW, Operand::FtU32L, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}} },
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{ InstrId::cpu_ldc1, { BinaryOpType::LD, Operand::FtU64, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Base, Operand::ImmS16 }}, true } },
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};
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const std::unordered_map<InstrId, ConditionalBranchOp> conditional_branch_ops {
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Loading…
Add table
Add a link
Reference in a new issue