mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-14 08:12:19 +00:00
Fix shifts and implement integer multiply and divide instructions in live generator
This commit is contained in:
Mr-Wiseguy
parent
a6c81e37df
commit
b7abe0ac4e
3 changed files with 215 additions and 20 deletions
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@ -27,6 +27,7 @@ namespace Registers {
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constexpr int arithmetic_temp1 = SLJIT_R0;
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constexpr int arithmetic_temp2 = SLJIT_R1;
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constexpr int arithmetic_temp3 = SLJIT_R2;
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constexpr int arithmetic_temp4 = SLJIT_R3;
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constexpr int float_temp = SLJIT_FR0;
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}
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@ -224,10 +225,17 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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get_operand_values(op.operands.operands[0], ctx, src1, src1w);
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get_operand_values(op.operands.operands[1], ctx, src2, src2w);
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// TODO
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assert(op.operands.operand_operations[0] == UnaryOpType::None || op.operands.operand_operations[0] == UnaryOpType::ToU64);
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assert(op.operands.operand_operations[1] == UnaryOpType::None);
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bool cmp_unsigned = op.operands.operand_operations[0] == UnaryOpType::ToU64;
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// TODO validate that the unary ops are valid for the current binary op.
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assert(op.operands.operand_operations[0] == UnaryOpType::None ||
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op.operands.operand_operations[0] == UnaryOpType::ToU64 ||
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op.operands.operand_operations[0] == UnaryOpType::ToS64 ||
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op.operands.operand_operations[0] == UnaryOpType::ToU32);
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assert(op.operands.operand_operations[1] == UnaryOpType::None ||
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op.operands.operand_operations[1] == UnaryOpType::Mask5 || // Only for 32-bit shifts
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op.operands.operand_operations[1] == UnaryOpType::Mask6); // Only for 64-bit shifts
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bool cmp_unsigned = op.operands.operand_operations[0] != UnaryOpType::ToS64;
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auto sign_extend_and_store = [dst, dstw, this]() {
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// Sign extend the result.
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@ -425,22 +433,32 @@ void N64Recomp::LiveGenerator::process_binary_op(const BinaryOp& op, const Instr
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do_op64(SLJIT_XOR);
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break;
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case BinaryOpType::Sll32:
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do_op32(SLJIT_SHL32);
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// TODO only mask if the second input's op is Mask5.
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do_op32(SLJIT_MSHL32);
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break;
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case BinaryOpType::Sll64:
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do_op64(SLJIT_SHL);
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// TODO only mask if the second input's op is Mask6.
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do_op64(SLJIT_MSHL);
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break;
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case BinaryOpType::Srl32:
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do_op32(SLJIT_LSHR32);
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// TODO only mask if the second input's op is Mask5.
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do_op32(SLJIT_MLSHR32);
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break;
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case BinaryOpType::Srl64:
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do_op64(SLJIT_LSHR);
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// TODO only mask if the second input's op is Mask6.
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do_op64(SLJIT_MLSHR);
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break;
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case BinaryOpType::Sra32:
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do_op32(SLJIT_ASHR32);
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// Hardware bug: The input is not masked to 32 bits before right shifting, so bits from the upper half of the register will bleed into the lower half.
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// This means we have to use a 64-bit shift and manually mask the input before shifting.
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// TODO only mask if the second input's op is Mask5.
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sljit_emit_op2(this->compiler, SLJIT_AND32, Registers::arithmetic_temp1, 0, src2, src2w, SLJIT_IMM, 0b11111);
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sljit_emit_op2(this->compiler, SLJIT_MASHR, Registers::arithmetic_temp1, 0, src1, src1w, Registers::arithmetic_temp1, 0);
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sign_extend_and_store();
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break;
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case BinaryOpType::Sra64:
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do_op64(SLJIT_ASHR);
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// TODO only mask if the second input's op is Mask6.
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do_op64(SLJIT_MASHR);
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break;
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// Comparisons
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@ -621,7 +639,7 @@ void N64Recomp::LiveGenerator::process_store_op(const StoreOp& op, const Instruc
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}
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void N64Recomp::LiveGenerator::emit_function_start(const std::string& function_name) const {
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sljit_emit_enter(compiler, 0, SLJIT_ARGS2V(P, P), 3, 2, 0);
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sljit_emit_enter(compiler, 0, SLJIT_ARGS2V(P, P), 4, 5, 0);
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sljit_emit_op2(compiler, SLJIT_SUB, Registers::rdram, 0, Registers::rdram, 0, SLJIT_IMM, 0xFFFFFFFF80000000);
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}
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@ -795,7 +813,167 @@ void N64Recomp::LiveGenerator::emit_cop1_cs_write(int reg) const {
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}
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void N64Recomp::LiveGenerator::emit_muldiv(InstrId instr_id, int reg1, int reg2) const {
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assert(false);
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sljit_sw src1;
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sljit_sw src1w;
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sljit_sw src2;
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sljit_sw src2w;
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get_gpr_values(reg1, src1, src1w);
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get_gpr_values(reg2, src2, src2w);
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auto do_mul32_op = [src1, src1w, src2, src2w, this](bool is_signed) {
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// Load the two inputs into the multiplication input registers (R0/R1).
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if (is_signed) {
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// 32-bit signed multiplication is really 64 bits * 35 bits, so load accordingly.
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sljit_emit_op1(compiler, SLJIT_MOV, SLJIT_R0, 0, src1, src1w);
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// Sign extend to 35 bits by shifting left by 64 - 35 and then shifting right by the same amount.
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sljit_emit_op2(compiler, SLJIT_SHL, SLJIT_R1, 0, src2, src2w, SLJIT_IMM, 64 - 35);
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sljit_emit_op2(compiler, SLJIT_ASHR, SLJIT_R1, 0, SLJIT_R1, 0, SLJIT_IMM, 64 - 35);
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}
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else {
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sljit_emit_op1(compiler, SLJIT_MOV_U32, SLJIT_R0, 0, src1, src1w);
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sljit_emit_op1(compiler, SLJIT_MOV_U32, SLJIT_R1, 0, src2, src2w);
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}
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// Perform the multiplication.
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sljit_emit_op0(compiler, is_signed ? SLJIT_LMUL_SW : SLJIT_LMUL_UW);
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// Move the results into hi and lo with sign extension.
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sljit_emit_op2(compiler, SLJIT_ASHR, Registers::hi, 0, SLJIT_R0, 0, SLJIT_IMM, 32);
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sljit_emit_op1(compiler, SLJIT_MOV_S32, Registers::lo, 0, SLJIT_R0, 0);
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};
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auto do_mul64_op = [src1, src1w, src2, src2w, this](bool is_signed) {
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// Load the two inputs into the multiplication input registers (R0/R1).
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sljit_emit_op1(compiler, SLJIT_MOV, SLJIT_R0, 0, src1, src1w);
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sljit_emit_op1(compiler, SLJIT_MOV, SLJIT_R1, 0, src2, src2w);
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// Perform the multiplication.
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sljit_emit_op0(compiler, is_signed ? SLJIT_LMUL_SW : SLJIT_LMUL_UW);
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// Move the results into hi and lo.
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sljit_emit_op1(compiler, SLJIT_MOV, Registers::hi, 0, SLJIT_R1, 0);
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sljit_emit_op1(compiler, SLJIT_MOV, Registers::lo, 0, SLJIT_R0, 0);
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};
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auto do_div_op = [src1, src1w, src2, src2w, this](bool doubleword, bool is_signed) {
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// Pick the division opcode based on the bit width and signedness.
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// Note that the 64-bit division opcode is used for 32-bit signed division to match hardware behavior and prevent overflow.
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sljit_sw div_opcode = doubleword ?
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(is_signed ? SLJIT_DIVMOD_SW : SLJIT_DIVMOD_UW) :
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(is_signed ? SLJIT_DIVMOD_SW : SLJIT_DIVMOD_U32);
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// Pick the move opcode to use for loading the operands.
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sljit_sw load_opcode = doubleword ? SLJIT_MOV :
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(is_signed ? SLJIT_MOV_S32 : SLJIT_MOV_U32);
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// Pick the move opcode to use for saving the results.
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sljit_sw save_opcode = doubleword ? SLJIT_MOV : SLJIT_MOV_S32;
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// Load the two inputs into R0 and R1 (the numerator and denominator).
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sljit_emit_op1(compiler, load_opcode, SLJIT_R0, 0, src1, src1w);
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// TODO figure out 32-bit signed division behavior when inputs aren't properly sign extended.
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// if (!doubleword && is_signed) {
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// // Sign extend to 35 bits by shifting left by 64 - 35 and then shifting right by the same amount.
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// sljit_emit_op2(compiler, SLJIT_SHL, SLJIT_R1, 0, src2, src2w, SLJIT_IMM, 64 - 35);
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// sljit_emit_op2(compiler, SLJIT_ASHR, SLJIT_R1, 0, SLJIT_R1, 0, SLJIT_IMM, 64 - 35);
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// }
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// else {
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sljit_emit_op1(compiler, load_opcode, SLJIT_R1, 0, src2, src2w);
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// }
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// Prevent overflow on 64-bit signed division.
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if (doubleword && is_signed) {
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// If the numerator is INT64_MIN and the denominator is -1, an overflow will occur. To prevent an exception and
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// behave as the original hardware would, check if either of those conditions are false.
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// If neither condition is false (i.e. both are true), set the denominator to 1.
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// Xor the numerator with INT64_MIN. This will be zero if they're equal.
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sljit_emit_op2(compiler, SLJIT_XOR, Registers::arithmetic_temp3, 0, Registers::arithmetic_temp1, 0, SLJIT_IMM, sljit_sw(INT64_MIN));
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// Invert the denominator. This will be zero if it's -1.
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sljit_emit_op2(compiler, SLJIT_XOR, Registers::arithmetic_temp4, 0, Registers::arithmetic_temp2, 0, SLJIT_IMM, sljit_sw(-1));
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// Or the results of the previous two calculations and set the zero flag. This will be zero if both conditions were met.
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sljit_emit_op2(compiler, SLJIT_OR | SLJIT_SET_Z, Registers::arithmetic_temp3, 0, Registers::arithmetic_temp3, 0, Registers::arithmetic_temp4, 0);
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// If the zero flag is 0, meaning both conditions were true, replace the denominator with 1.
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// i.e. conditionally move an immediate of 1 into arithmetic temp 2 if the zero flag is 0.
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sljit_emit_select(compiler, SLJIT_ZERO, SLJIT_R1, SLJIT_IMM, 1, SLJIT_R1);
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}
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// If the denominator is 0, skip the division and jump the special handling for that case.
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// Set the zero flag if the denominator is zero by AND'ing it with itself.
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sljit_emit_op2u(compiler, SLJIT_AND | SLJIT_SET_Z, SLJIT_R1, 0, SLJIT_R1, 0);
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// Branch past the division if the zero flag is 0.
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sljit_jump* jump_skip_division = sljit_emit_jump(compiler, SLJIT_ZERO);
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// Perform the division.
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sljit_emit_op0(compiler, div_opcode);
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// Extract the remainder and quotient into the high and low registers respectively.
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sljit_emit_op1(compiler, save_opcode, Registers::hi, 0, SLJIT_R1, 0);
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sljit_emit_op1(compiler, save_opcode, Registers::lo, 0, SLJIT_R0, 0);
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// Jump to the end of this routine.
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sljit_jump* jump_to_end = sljit_emit_jump(compiler, SLJIT_JUMP);
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// Emit a label and set it as the target of the jump if the denominator was zero.
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sljit_label* after_division = sljit_emit_label(compiler);
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sljit_set_label(jump_skip_division, after_division);
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// Move the numerator into hi.
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sljit_emit_op1(compiler, SLJIT_MOV, Registers::hi, 0, SLJIT_R0, 0);
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if (is_signed) {
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// Calculate the negative signum of the numerator and place it in lo.
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// neg_signum = ((int64_t)(~x) >> (bit width - 1)) | 1
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sljit_emit_op2(compiler, SLJIT_XOR, Registers::lo, 0, SLJIT_R0, 0, SLJIT_IMM, sljit_sw(-1));
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sljit_emit_op2(compiler, SLJIT_ASHR, Registers::lo, 0, Registers::lo, 0, SLJIT_IMM, 64 - 1);
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sljit_emit_op2(compiler, SLJIT_OR, Registers::lo, 0, Registers::lo, 0, SLJIT_IMM, 1);
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}
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else {
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// Move -1 into lo.
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sljit_emit_op1(compiler, SLJIT_MOV, Registers::lo, 0, SLJIT_IMM, -1);
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}
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// Emit a label and set it as the target of the jump after the divison.
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sljit_label* end_label = sljit_emit_label(compiler);
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sljit_set_label(jump_to_end, end_label);
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};
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switch (instr_id) {
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case InstrId::cpu_mult:
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do_mul32_op(true);
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break;
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case InstrId::cpu_multu:
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do_mul32_op(false);
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break;
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case InstrId::cpu_dmult:
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do_mul64_op(true);
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break;
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case InstrId::cpu_dmultu:
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do_mul64_op(false);
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break;
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case InstrId::cpu_div:
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do_div_op(false, true);
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break;
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case InstrId::cpu_divu:
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do_div_op(false, false);
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break;
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case InstrId::cpu_ddiv:
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do_div_op(true, true);
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break;
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case InstrId::cpu_ddivu:
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do_div_op(true, false);
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break;
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default:
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assert(false);
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break;
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}
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}
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void N64Recomp::LiveGenerator::emit_syscall(uint32_t instr_vram) const {
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@ -194,6 +194,8 @@ int main(int argc, const char** argv) {
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int count = argc - 1 - 1;
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int passed_count = 0;
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std::vector<size_t> failed_tests{};
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for (size_t test_index = 0; test_index < count; test_index++) {
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const char* cur_test_name = argv[2 + test_index];
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printf("Running test: %s\n", cur_test_name);
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@ -216,9 +218,26 @@ int main(int argc, const char** argv) {
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printf(" Output data did not match, dumped to file\n");
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break;
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}
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if (stats.error != TestError::Success) {
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failed_tests.emplace_back(test_index);
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}
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printf("\n");
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}
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printf("Passed %d/%d tests\n", passed_count, count);
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if (!failed_tests.empty()) {
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printf(" Failed: ");
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for (size_t i = 0; i < failed_tests.size(); i++) {
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size_t test_index = failed_tests[i];
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printf("%s", argv[2 + test_index]);
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if (i != failed_tests.size() - 1) {
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printf(", ");
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}
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}
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printf("\n");
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}
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return 0;
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}
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@ -65,24 +65,22 @@ namespace N64Recomp {
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{ InstrId::cpu_ori, { BinaryOpType::Or64, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Rs, Operand::ImmU16 }}} },
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{ InstrId::cpu_xori, { BinaryOpType::Xor64, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Rs, Operand::ImmU16 }}} },
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// Shifts
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/* BUG Should mask after (change op to Sll32 and input op to ToU32) */
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{ InstrId::cpu_sllv, { BinaryOpType::Sll64, Operand::Rd, {{ UnaryOpType::ToS32, UnaryOpType::Mask5 }, { Operand::Rt, Operand::Rs }}} },
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{ InstrId::cpu_sllv, { BinaryOpType::Sll32, Operand::Rd, {{ UnaryOpType::None, UnaryOpType::Mask5 }, { Operand::Rt, Operand::Rs }}} },
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{ InstrId::cpu_dsllv, { BinaryOpType::Sll64, Operand::Rd, {{ UnaryOpType::None, UnaryOpType::Mask6 }, { Operand::Rt, Operand::Rs }}} },
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{ InstrId::cpu_srlv, { BinaryOpType::Srl32, Operand::Rd, {{ UnaryOpType::ToU32, UnaryOpType::Mask5 }, { Operand::Rt, Operand::Rs }}} },
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{ InstrId::cpu_dsrlv, { BinaryOpType::Srl64, Operand::Rd, {{ UnaryOpType::ToU64, UnaryOpType::Mask6 }, { Operand::Rt, Operand::Rs }}} },
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/* BUG Should mask after (change op to Sra32 and input op to ToS64) */
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{ InstrId::cpu_srav, { BinaryOpType::Sra64, Operand::Rd, {{ UnaryOpType::ToS32, UnaryOpType::Mask5 }, { Operand::Rt, Operand::Rs }}} },
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// Hardware bug: The input is not masked to 32 bits before right shifting, so bits from the upper half of the register will bleed into the lower half.
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{ InstrId::cpu_srav, { BinaryOpType::Sra32, Operand::Rd, {{ UnaryOpType::ToS64, UnaryOpType::Mask5 }, { Operand::Rt, Operand::Rs }}} },
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{ InstrId::cpu_dsrav, { BinaryOpType::Sra64, Operand::Rd, {{ UnaryOpType::ToS64, UnaryOpType::Mask6 }, { Operand::Rt, Operand::Rs }}} },
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// Shifts (immediate)
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/* BUG Should mask after (change op to Sll32 and input op to ToU32) */
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{ InstrId::cpu_sll, { BinaryOpType::Sll64, Operand::Rd, {{ UnaryOpType::ToS32, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_sll, { BinaryOpType::Sll32, Operand::Rd, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsll, { BinaryOpType::Sll64, Operand::Rd, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsll32, { BinaryOpType::Sll64, Operand::Rd, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Rt, Operand::Sa32 }}} },
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{ InstrId::cpu_srl, { BinaryOpType::Srl32, Operand::Rd, {{ UnaryOpType::ToU32, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsrl, { BinaryOpType::Srl64, Operand::Rd, {{ UnaryOpType::ToU64, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsrl32, { BinaryOpType::Srl64, Operand::Rd, {{ UnaryOpType::ToU64, UnaryOpType::None }, { Operand::Rt, Operand::Sa32 }}} },
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/* BUG should cast after (change op to Sra32 and input op to ToS64) */
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{ InstrId::cpu_sra, { BinaryOpType::Sra64, Operand::Rd, {{ UnaryOpType::ToS32, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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// Hardware bug: The input is not masked to 32 bits before right shifting, so bits from the upper half of the register will bleed into the lower half.
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{ InstrId::cpu_sra, { BinaryOpType::Sra32, Operand::Rd, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsra, { BinaryOpType::Sra64, Operand::Rd, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rt, Operand::Sa }}} },
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{ InstrId::cpu_dsra32, { BinaryOpType::Sra64, Operand::Rd, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rt, Operand::Sa32 }}} },
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// Comparisons
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Loading…
Add table
Reference in a new issue