Mirrors/N64Recomp
1
0
Fork 0
mirror of https://github.com/N64Recomp/N64Recomp.git synced 2025-05-14 08:12:19 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fixed likely swap on bgezal, fixed extra indent branch close and missing

Browse source 
indent on branch statement
This commit is contained in:
Mr-Wiseguy 2024-06-06 23:58:02 -04:00
parent 3167fadd47
commit c3de49c944
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/recompilation.cpp
View file

@ -216,8 +216,8 @@ const std::unordered_map<InstrId, ConditionalBranchOp> conditional_branch_ops {
{ InstrId::cpu_blezl, { BinaryOpType::LessEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, true }}, { InstrId::cpu_blezl, { BinaryOpType::LessEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, true }},
{ InstrId::cpu_bltz, { BinaryOpType::Less, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, false }}, { InstrId::cpu_bltz, { BinaryOpType::Less, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, false }},
{ InstrId::cpu_bltzl, { BinaryOpType::Less, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, true }}, { InstrId::cpu_bltzl, { BinaryOpType::Less, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, false, true }},
{ InstrId::cpu_bgezall, { BinaryOpType::GreaterEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, true, false }}, { InstrId::cpu_bgezal, { BinaryOpType::GreaterEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, true, false }},
{ InstrId::cpu_bgezal, { BinaryOpType::GreaterEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, true, true }}, { InstrId::cpu_bgezall, { BinaryOpType::GreaterEq, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::Zero }}, true, true }},
{ InstrId::cpu_bc1f, { BinaryOpType::NotEqual, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, false }}, { InstrId::cpu_bc1f, { BinaryOpType::NotEqual, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, false }},
{ InstrId::cpu_bc1fl, { BinaryOpType::NotEqual, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, true }}, { InstrId::cpu_bc1fl, { BinaryOpType::NotEqual, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, true }},
{ InstrId::cpu_bc1t, { BinaryOpType::Equal, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, false }}, { InstrId::cpu_bc1t, { BinaryOpType::Equal, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::Cop1cs, Operand::Zero }}, false, false }},
@ -1462,6 +1462,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
print_indent(); print_indent();
generator.emit_branch_condition(output_file, find_conditional_branch_it->second, instruction_context); generator.emit_branch_condition(output_file, find_conditional_branch_it->second, instruction_context);
print_indent();
if (find_conditional_branch_it->second.link) { if (find_conditional_branch_it->second.link) {
print_func_call(instr.getBranchVramGeneric()); print_func_call(instr.getBranchVramGeneric());
} }
@ -1469,7 +1470,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
print_branch((uint32_t)instr.getBranchVramGeneric()); print_branch((uint32_t)instr.getBranchVramGeneric());
} }
print_indent();
generator.emit_branch_close(output_file); generator.emit_branch_close(output_file);
is_branch_likely = find_conditional_branch_it->second.likely; is_branch_likely = find_conditional_branch_it->second.likely;