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https://github.com/N64Recomp/N64Recomp.git
synced 2025-05-14 08:12:19 +00:00
Add operands for other uses of float registers
This commit is contained in:
Mr-Wiseguy
parent
c3de49c944
commit
d91f1cf3a8
1 changed files with 94 additions and 45 deletions
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@ -84,6 +84,21 @@ enum class Operand {
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Fd, // FPR
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Fs, // FPR
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Ft, // FPR
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FdDouble, // Double float in fd FPR
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FsDouble, // Double float in fs FPR
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FtDouble, // Double float in ft FPR
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// Raw low 32-bit values of FPRs with handling for mips3 float mode behavior
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FdU32L,
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FsU32L,
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FtU32L,
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// Raw high 32-bit values of FPRs with handling for mips3 float mode behavior
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FdU32H,
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FsU32H,
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FtU32H,
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// Raw 64-bit values of FPRs
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FdU64,
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FsU64,
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FtU64,
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ImmU16, // 16-bit immediate, unsigned
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ImmS16, // 16-bit immediate, signed
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Sa, // Shift amount
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@ -135,6 +150,8 @@ const std::unordered_map<InstrId, UnaryOp> unary_ops {
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{ InstrId::cpu_mtlo, { UnaryOpType::None, Operand::Lo, Operand::Rs } },
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{ InstrId::cpu_mfhi, { UnaryOpType::None, Operand::Rd, Operand::Hi } },
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{ InstrId::cpu_mflo, { UnaryOpType::None, Operand::Rd, Operand::Lo } },
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{ InstrId::cpu_mtc1, { UnaryOpType::None, Operand::FsU32L, Operand::Rt } },
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{ InstrId::cpu_mfc1, { UnaryOpType::ToInt32, Operand::Rt, Operand::FsU32L } },
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};
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const std::unordered_map<InstrId, BinaryOp> binary_ops {
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@ -190,17 +207,19 @@ const std::unordered_map<InstrId, BinaryOp> binary_ops {
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{ InstrId::cpu_slti, { BinaryOpType::Less, Operand::Rt, {{ UnaryOpType::ToS64, UnaryOpType::None }, { Operand::Rs, Operand::ImmS16 }}} },
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{ InstrId::cpu_sltiu, { BinaryOpType::Less, Operand::Rt, {{ UnaryOpType::ToU64, UnaryOpType::None }, { Operand::Rs, Operand::ImmS16 }}} },
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// Loads
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{ InstrId::cpu_ld, { BinaryOpType::LD, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lw, { BinaryOpType::LW, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwu, { BinaryOpType::LWU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lh, { BinaryOpType::LH, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lhu, { BinaryOpType::LHU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lb, { BinaryOpType::LB, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lbu, { BinaryOpType::LBU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldl, { BinaryOpType::LDL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldr, { BinaryOpType::LDR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwl, { BinaryOpType::LWL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwr, { BinaryOpType::LWR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ld, { BinaryOpType::LD, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lw, { BinaryOpType::LW, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwu, { BinaryOpType::LWU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lh, { BinaryOpType::LH, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lhu, { BinaryOpType::LHU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lb, { BinaryOpType::LB, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lbu, { BinaryOpType::LBU, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldl, { BinaryOpType::LDL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldr, { BinaryOpType::LDR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwl, { BinaryOpType::LWL, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwr, { BinaryOpType::LWR, Operand::Rt, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_lwc1, { BinaryOpType::LW, Operand::FtU32L, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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{ InstrId::cpu_ldc1, { BinaryOpType::LD, Operand::FtU64, {{ UnaryOpType::None, UnaryOpType::None }, { Operand::ImmS16, Operand::Base }}} },
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};
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const std::unordered_map<InstrId, ConditionalBranchOp> conditional_branch_ops {
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@ -321,6 +340,27 @@ std::string gpr_to_string(int gpr_index) {
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return fmt::format("ctx->r{}", gpr_index);
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}
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std::string fpr_to_string(int fpr_index) {
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return fmt::format("ctx->f{}.fl", fpr_index);
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}
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std::string fpr_double_to_string(int fpr_index) {
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return fmt::format("ctx->f{}.d", fpr_index);
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}
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std::string fpr_u32l_to_string(int fpr_index) {
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if (fpr_index & 1) {
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return fmt::format("ctx->f_odd[({} - 1) * 2]", fpr_index);
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}
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else {
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return fmt::format("ctx->f{}.u32l", fpr_index);
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}
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}
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std::string fpr_u64_to_string(int fpr_index) {
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return fmt::format("ctx->f{}.u64", fpr_index);
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}
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std::string unsigned_reloc(const InstructionContext& context) {
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switch (context.reloc_type) {
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case RecompPort::RelocType::R_MIPS_HI16:
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@ -348,14 +388,50 @@ void CGenerator::get_operand_string(Operand operand, UnaryOpType operation, cons
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operand_string = gpr_to_string(context.rt);
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break;
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case Operand::Fd:
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assert(false);
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operand_string = fpr_to_string(context.fd);
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break;
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case Operand::Fs:
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assert(false);
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operand_string = fpr_to_string(context.fs);
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break;
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case Operand::Ft:
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operand_string = fpr_to_string(context.ft);
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break;
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case Operand::FdDouble:
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operand_string = fpr_double_to_string(context.fd);
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break;
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case Operand::FsDouble:
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operand_string = fpr_double_to_string(context.fs);
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break;
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case Operand::FtDouble:
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operand_string = fpr_double_to_string(context.ft);
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break;
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case Operand::FdU32L:
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operand_string = fpr_u32l_to_string(context.fd);
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break;
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case Operand::FsU32L:
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operand_string = fpr_u32l_to_string(context.fs);
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break;
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case Operand::FtU32L:
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operand_string = fpr_u32l_to_string(context.ft);
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break;
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case Operand::FdU32H:
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assert(false);
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break;
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case Operand::FsU32H:
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assert(false);
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break;
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case Operand::FtU32H:
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assert(false);
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break;
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case Operand::FdU64:
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operand_string = fpr_u64_to_string(context.fd);
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break;
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case Operand::FsU64:
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operand_string = fpr_u64_to_string(context.fs);
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break;
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case Operand::FtU64:
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operand_string = fpr_u64_to_string(context.ft);
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break;
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case Operand::ImmU16:
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if (context.reloc_type != RecompPort::RelocType::R_MIPS_NONE) {
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operand_string = unsigned_reloc(context);
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@ -499,6 +575,11 @@ void CGenerator::process_binary_op(std::ostream& output_file, const BinaryOp& op
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get_operand_string(op.output, UnaryOpType::None, ctx, output);
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get_binary_expr_string(op.type, op.operands, ctx, output, expression);
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// TODO remove this after the refactor is done, temporary hack to match the old recompiler output.
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if (op.type == BinaryOpType::LD && op.output == Operand::FtU64) {
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fmt::print(output_file, "CHECK_FR(ctx, {});\n ", ctx.ft);
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}
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fmt::print(output_file, "{} = {};\n", output, expression);
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}
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@ -1044,25 +1125,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
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break;
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// Cop1 loads/stores
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case InstrId::cpu_mtc1:
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if ((fs & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = {}{}", fs, ctx_gpr_prefix(rt), rt);
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}
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else {
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// odd fpr
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print_line("ctx->f_odd[({} - 1) * 2] = {}{}", fs, ctx_gpr_prefix(rt), rt);
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}
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break;
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case InstrId::cpu_mfc1:
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if ((fs & 1) == 0) {
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// even fpr
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print_line("{}{} = (int32_t)ctx->f{}.u32l", ctx_gpr_prefix(rt), rt, fs);
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} else {
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// odd fpr
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print_line("{}{} = (int32_t)ctx->f_odd[({} - 1) * 2]", ctx_gpr_prefix(rt), rt, fs);
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}
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break;
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//case InstrId::cpu_dmfc1:
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// if ((fs & 1) == 0) {
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// // even fpr
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@ -1072,19 +1134,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
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// return false;
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// }
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// break;
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case InstrId::cpu_lwc1:
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if ((ft & 1) == 0) {
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// even fpr
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print_line("ctx->f{}.u32l = MEM_W({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
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} else {
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// odd fpr
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print_line("ctx->f_odd[({} - 1) * 2] = MEM_W({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
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}
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break;
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case InstrId::cpu_ldc1:
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print_line("CHECK_FR(ctx, {})", ft);
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print_line("ctx->f{}.u64 = LD({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
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break;
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case InstrId::cpu_swc1:
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if ((ft & 1) == 0) {
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// even fpr
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