Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
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gdkchan
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10 changed files with 1122 additions and 399 deletions
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@ -47,6 +47,18 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<byte> _8BIT_IMM_()
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{
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yield return 0x00;
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@ -79,6 +91,48 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Bic_Orr_Vi_16bit_()
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{
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return new uint[]
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{
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0x2F009400u, // BIC V0.4H, #0
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0x0F009400u // ORR V0.4H, #0
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};
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}
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private static uint[] _Bic_Orr_Vi_32bit_()
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{
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return new uint[]
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{
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0x2F001400u, // BIC V0.2S, #0
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0x0F001400u // ORR V0.2S, #0
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};
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}
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private static uint[] _F_Mov_Vi_2S_()
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{
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return new uint[]
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{
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0x0F00F400u // FMOV V0.2S, #2.0
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};
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}
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private static uint[] _F_Mov_Vi_4S_()
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{
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return new uint[]
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{
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0x4F00F400u // FMOV V0.4S, #2.0
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};
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}
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private static uint[] _F_Mov_Vi_2D_()
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{
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return new uint[]
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{
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0x6F00F400u // FMOV V0.2D, #2.0
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};
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}
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private static uint[] _Movi_V_8bit_()
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{
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return new uint[]
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@ -131,19 +185,105 @@ namespace Ryujinx.Tests.Cpu
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntImm8 = 2;
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private const int RndCntImm64 = 2;
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[Test, Pairwise]
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public void Bic_Orr_Vi_16bit([ValueSource("_Bic_Orr_Vi_16bit_")] uint opcodes,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 13);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Bic_Orr_Vi_32bit([ValueSource("_Bic_Orr_Vi_32bit_")] uint opcodes,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 3) << 13);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2S([ValueSource("_F_Mov_Vi_2S_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE1(z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_4S([ValueSource("_F_Mov_Vi_4S_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2D([ValueSource("_F_Mov_Vi_2D_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_V_8bit([ValueSource("_Movi_V_8bit_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((q & 1) << 30);
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@ -157,7 +297,6 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise]
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public void Movi_Mvni_V_16bit_shifted_imm([ValueSource("_Movi_Mvni_V_16bit_shifted_imm_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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@ -165,7 +304,6 @@ namespace Ryujinx.Tests.Cpu
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 13);
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opcodes |= ((q & 1) << 30);
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@ -180,7 +318,6 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifted_imm([ValueSource("_Movi_Mvni_V_32bit_shifted_imm_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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@ -188,7 +325,6 @@ namespace Ryujinx.Tests.Cpu
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 3) << 13);
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opcodes |= ((q & 1) << 30);
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@ -203,7 +339,6 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifting_ones([ValueSource("_Movi_Mvni_V_32bit_shifting_ones_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <8, 16>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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@ -211,7 +346,6 @@ namespace Ryujinx.Tests.Cpu
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 12);
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opcodes |= ((q & 1) << 30);
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@ -226,7 +360,6 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise]
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public void Movi_V_64bit_scalar([ValueSource("_Movi_V_64bit_scalar_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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@ -234,7 +367,6 @@ namespace Ryujinx.Tests.Cpu
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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@ -247,7 +379,6 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise]
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public void Movi_V_64bit_vector([ValueSource("_Movi_V_64bit_vector_")] uint opcodes,
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[Values(0u)] uint rd,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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@ -255,7 +386,6 @@ namespace Ryujinx.Tests.Cpu
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= ((rd & 31) << 0);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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