Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
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@ -73,7 +73,8 @@ namespace Ryujinx.Tests.Cpu
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCnt = 2;
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private const int RndCntIndex = 2;
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes,
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@ -83,7 +84,7 @@ namespace Ryujinx.Tests.Cpu
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint index,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint h = (index >> 2) & 1;
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@ -138,7 +139,7 @@ namespace Ryujinx.Tests.Cpu
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint index,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
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{
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uint h = (index >> 2) & 1;
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