Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
This commit is contained in:
LDj3SNuD
gdkchan
parent
ba86a5d7f3
commit
10c74182ba
10 changed files with 1122 additions and 399 deletions
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@ -212,6 +212,51 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _Shl_Sli_S_D_()
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{
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return new uint[]
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{
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0x5F405400u, // SHL D0, D0, #0
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//0x7F405400u // SLI D0, D0, #0
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};
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}
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private static uint[] _Shl_Sli_V_8B_16B_()
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{
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return new uint[]
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{
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0x0F085400u, // SHL V0.8B, V0.8B, #0
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0x2F085400u // SLI V0.8B, V0.8B, #0
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};
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}
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private static uint[] _Shl_Sli_V_4H_8H_()
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{
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return new uint[]
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{
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0x0F105400u, // SHL V0.4H, V0.4H, #0
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0x2F105400u // SLI V0.4H, V0.4H, #0
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};
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}
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private static uint[] _Shl_Sli_V_2S_4S_()
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{
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return new uint[]
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{
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0x0F205400u, // SHL V0.2S, V0.2S, #0
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0x2F205400u // SLI V0.2S, V0.2S, #0
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};
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}
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private static uint[] _Shl_Sli_V_2D_()
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{
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return new uint[]
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{
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0x4F405400u, // SHL V0.2D, V0.2D, #0
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0x6F405400u // SLI V0.2D, V0.2D, #0
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};
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}
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private static uint[] _SU_Shll_V_8B8H_16B8H_()
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{
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return new uint[]
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@ -516,113 +561,113 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
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}
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[Test, Pairwise, Description("SHL <V><d>, <V><n>, #<shift>")]
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public void Shl_S_D([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
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[Test, Pairwise]
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public void Shl_Sli_S_D([ValueSource("_Shl_Sli_S_D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
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{
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uint immHb = (64 + shift) & 0x7F;
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uint opcode = 0x5F405400; // SHL D0, D0, #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (immHb << 16);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
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public void Shl_V_8B_16B([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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[Test, Pairwise]
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public void Shl_Sli_V_8B_16B([ValueSource("_Shl_Sli_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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uint immHb = (8 + shift) & 0x7F;
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uint opcode = 0x0F085400; // SHL V0.8B, V0.8B, #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (immHb << 16);
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opcode |= ((q & 1) << 30);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
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public void Shl_V_4H_8H([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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[Test, Pairwise]
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public void Shl_Sli_V_4H_8H([ValueSource("_Shl_Sli_V_4H_8H_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint immHb = (16 + shift) & 0x7F;
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uint opcode = 0x0F105400; // SHL V0.4H, V0.4H, #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (immHb << 16);
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opcode |= ((q & 1) << 30);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
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public void Shl_V_2S_4S([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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[Test, Pairwise]
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public void Shl_Sli_V_2S_4S([ValueSource("_Shl_Sli_V_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint immHb = (32 + shift) & 0x7F;
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uint opcode = 0x0F205400; // SHL V0.2S, V0.2S, #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (immHb << 16);
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opcode |= ((q & 1) << 30);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
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public void Shl_V_2D([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
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[Test, Pairwise]
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public void Shl_Sli_V_2D([ValueSource("_Shl_Sli_V_2D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
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{
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uint immHb = (64 + shift) & 0x7F;
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uint opcode = 0x4F405400; // SHL V0.2D, V0.2D, #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (immHb << 16);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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