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Add ARM32 support on the translator (#561)

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* Remove ARM32 interpreter and add ARM32 support on the translator

* Nits.

* Rename Cond -> Condition

* Align code again

* Rename Data to Alu

* Enable ARM32 support and handle undefined instructions

* Use the IsThumb method to check if its a thumb opcode

* Remove another 32-bits check
This commit is contained in:
gdkchan 2019-01-24 23:59:53 -02:00 • committed by GitHub
parent 72157e03eb
commit 36b9ab0e48
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GPG key ID: 4AEE18F83AFDEB23
57 changed files with 1274 additions and 495 deletions
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15
ChocolArm64/State/Aarch32Mode.cs Normal file
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@ -0,0 +1,15 @@
namespace ChocolArm64.State
{
enum Aarch32Mode
{
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Monitor = 0b10110,
Abort = 0b10111,
Hypervisor = 0b11010,
Undefined = 0b11011,
System = 0b11111
}
}

28
ChocolArm64/State/CpuThreadState.cs
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@ -8,25 +8,13 @@ namespace ChocolArm64.State
{
public class CpuThreadState
{
internal const int LrIndex = 30;
internal const int ZrIndex = 31;
internal const int ErgSizeLog2 = 4;
internal const int DczSizeLog2 = 4;
private const int MinInstForCheck = 4000000;
internal ExecutionMode ExecutionMode;
//AArch32 state.
public uint R0, R1, R2, R3,
R4, R5, R6, R7,
R8, R9, R10, R11,
R12, R13, R14, R15;
public bool Thumb;
//AArch64 state.
public ulong X0, X1, X2, X3, X4, X5, X6, X7,
X8, X9, X10, X11, X12, X13, X14, X15,
X16, X17, X18, X19, X20, X21, X22, X23,
@ -42,6 +30,10 @@ namespace ChocolArm64.State
public bool Zero;
public bool Negative;
public bool IsAarch32;
public int ElrHyp;
public bool Running { get; set; }
public int Core { get; set; }
@ -146,6 +138,18 @@ namespace ChocolArm64.State
Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode));
}
internal ExecutionMode GetExecutionMode()
{
if (!IsAarch32)
{
return ExecutionMode.Aarch64;
}
else
{
return Thumb ? ExecutionMode.Aarch32Thumb : ExecutionMode.Aarch32Arm;
}
}
internal bool GetFpcrFlag(Fpcr flag)
{
return (Fpcr & (1 << (int)flag)) != 0;

5
ChocolArm64/State/ExecutionMode.cs
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@ -2,7 +2,8 @@ namespace ChocolArm64.State
{
enum ExecutionMode
{
AArch32,
AArch64
Aarch64,
Aarch32Arm,
Aarch32Thumb
}
}

4
ChocolArm64/State/PState.cs
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@ -5,11 +5,15 @@ namespace ChocolArm64.State
[Flags]
enum PState
{
TBit = 5,
VBit = 28,
CBit = 29,
ZBit = 30,
NBit = 31,
T = 1 << TBit,
V = 1 << VBit,
C = 1 << CBit,
Z = 1 << ZBit,

2
ChocolArm64/State/Register.cs
View file

@ -43,6 +43,8 @@ namespace ChocolArm64.State
{
switch ((PState)Index)
{
case PState.TBit: return GetField(nameof(CpuThreadState.Thumb));
case PState.VBit: return GetField(nameof(CpuThreadState.Overflow));
case PState.CBit: return GetField(nameof(CpuThreadState.Carry));
case PState.ZBit: return GetField(nameof(CpuThreadState.Zero));

41
ChocolArm64/State/RegisterAlias.cs Normal file
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@ -0,0 +1,41 @@
namespace ChocolArm64.State
{
static class RegisterAlias
{
public const int R8Usr = 8;
public const int R9Usr = 9;
public const int R10Usr = 10;
public const int R11Usr = 11;
public const int R12Usr = 12;
public const int SpUsr = 13;
public const int LrUsr = 14;
public const int SpHyp = 15;
public const int LrIrq = 16;
public const int SpIrq = 17;
public const int LrSvc = 18;
public const int SpSvc = 19;
public const int LrAbt = 20;
public const int SpAbt = 21;
public const int LrUnd = 22;
public const int SpUnd = 23;
public const int R8Fiq = 24;
public const int R9Fiq = 25;
public const int R10Fiq = 26;
public const int R11Fiq = 27;
public const int R12Fiq = 28;
public const int SpFiq = 29;
public const int LrFiq = 30;
public const int Aarch32Lr = 14;
public const int Aarch32Pc = 15;
public const int Lr = 30;
public const int Zr = 31;
}
}