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Misc. CPU improvements (#519)

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* Fix and simplify TranslatorCache

* Fix some assignment alignments, remove some unused usings

* Changes to ILEmitter, separate it from ILEmitterCtx

* Rename ILEmitter to ILMethodBuilder

* Rename LdrLit and *_Fix opcodes

* Revert TranslatorCache impl to the more performant one, fix a few issues with it

* Allow EmitOpCode to be called even after everything has been emitted

* Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point

* Remove unneeded temp use

* Add missing exit call on TestExclusive

* Use better hash

* Implement the == and != operators
This commit is contained in:
gdkchan 2018-12-10 22:58:52 -02:00 • committed by GitHub
parent f1529b1bc2
commit 36e8e074c9
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GPG key ID: 4AEE18F83AFDEB23
41 changed files with 943 additions and 915 deletions
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40
ChocolArm64/Translation/ILBlock.cs
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@ -14,19 +14,21 @@ namespace ChocolArm64.Translation
public bool HasStateStore { get; private set; }
public List<IILEmit> IlEmitters { get; private set; }
private List<IILEmit> _emitters;
public int Count => _emitters.Count;
public ILBlock Next { get; set; }
public ILBlock Branch { get; set; }
public ILBlock()
{
IlEmitters = new List<IILEmit>();
_emitters = new List<IILEmit>();
}
public void Add(IILEmit ilEmitter)
public void Add(IILEmit emitter)
{
if (ilEmitter is ILBarrier)
if (emitter is ILBarrier)
{
//Those barriers are used to separate the groups of CIL
//opcodes emitted by each ARM instruction.
@ -35,7 +37,7 @@ namespace ChocolArm64.Translation
IntAwOutputs = IntOutputs;
VecAwOutputs = VecOutputs;
}
else if (ilEmitter is IlOpCodeLoad ld && ILEmitter.IsRegIndex(ld.Index))
else if (emitter is ILOpCodeLoad ld && ILMethodBuilder.IsRegIndex(ld.Index))
{
switch (ld.IoType)
{
@ -44,30 +46,26 @@ namespace ChocolArm64.Translation
case IoType.Vector: VecInputs |= (1L << ld.Index) & ~VecAwOutputs; break;
}
}
else if (ilEmitter is IlOpCodeStore st)
else if (emitter is ILOpCodeStore st && ILMethodBuilder.IsRegIndex(st.Index))
{
if (ILEmitter.IsRegIndex(st.Index))
switch (st.IoType)
{
switch (st.IoType)
{
case IoType.Flag: IntOutputs |= (1L << st.Index) << 32; break;
case IoType.Int: IntOutputs |= 1L << st.Index; break;
case IoType.Vector: VecOutputs |= 1L << st.Index; break;
}
}
if (st.IoType == IoType.Fields)
{
HasStateStore = true;
case IoType.Flag: IntOutputs |= (1L << st.Index) << 32; break;
case IoType.Int: IntOutputs |= 1L << st.Index; break;
case IoType.Vector: VecOutputs |= 1L << st.Index; break;
}
}
else if (emitter is ILOpCodeStoreState)
{
HasStateStore = true;
}
IlEmitters.Add(ilEmitter);
_emitters.Add(emitter);
}
public void Emit(ILEmitter context)
public void Emit(ILMethodBuilder context)
{
foreach (IILEmit ilEmitter in IlEmitters)
foreach (IILEmit ilEmitter in _emitters)
{
ilEmitter.Emit(context);
}