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Add MLS (vector) instruction, fix mistake introduced on last commit

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This commit is contained in:
gdkchan 2018-02-18 02:13:42 -03:00
parent c3b5b4ffeb
commit 3872ae034d
3 changed files with 19 additions and 5 deletions
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11
Ryujinx/Cpu/Instruction/AInstEmitSimdHelper.cs
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@ -210,14 +210,14 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpByElemF(Context, Emit, Op.Index);
EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: false);
}
public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpByElemF(Context, Emit, Op.Index);
EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: true);
}
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
@ -256,7 +256,7 @@ namespace ChocolArm64.Instruction
}
}
public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem)
public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -266,6 +266,11 @@ namespace ChocolArm64.Instruction
for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
{
if (Ternary)
{
EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
}
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);