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Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)

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* Added some 32 bits instructions:

* VBIC
* VTST
* VSRA

* Incremented the PTC

* Add tests and fix implementation

* Fixed VBIC immediate opcode mapping

* Hey hey!

* Nit.

Co-authored-by: gdkchan <gab.dark.100@gmail.com>
Co-authored-by: LDj3SNuD <dvitiello@gmail.com>
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
This commit is contained in:
Valentin PONS 2020-07-19 14:11:58 -04:00 • committed by GitHub
parent 9d65de74fc
commit 3af2ce74ec
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10 changed files with 361 additions and 66 deletions
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21
ARMeilleure/Instructions/InstEmitSimdShift32.cs
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@ -129,6 +129,27 @@ namespace ARMeilleure.Instructions
EmitVectorUnaryNarrowOp32(context, (op1) => context.ShiftRightUI(op1, Const(shift)));
}
public static void Vsra(ArmEmitterContext context)
{
OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
int shift = GetImmShr(op);
int maxShift = (8 << op.Size) - 1;
if (op.U)
{
EmitVectorImmBinaryQdQmOpZx32(context, (op1, op2) =>
{
Operand shiftRes = shift > maxShift ? Const(op2.Type, 0) : context.ShiftRightUI(op2, Const(shift));
return context.Add(op1, shiftRes);
});
}
else
{
EmitVectorImmBinaryQdQmOpSx32(context, (op1, op2) => context.Add(op1, context.ShiftRightSI(op2, Const(Math.Min(maxShift, shift)))));
}
}
private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned)
{
if (shiftLsB.Type == OperandType.I64)