Fix FMUL and TEXS shader instructions (#347)
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parent
6e48312052
commit
4f499b6845
2 changed files with 87 additions and 51 deletions
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@ -26,8 +26,8 @@ namespace Ryujinx.Graphics.Gal.Shader
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private static int[,] MaskLut = new int[,]
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{
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{ ____, ____, ____, ____, ____, ____, ____, ____ },
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{ R___, _G__, __B_, ___A, RG__, ____, ____, ____ },
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{ R___, _G__, __B_, ___A, RG__, R__A, _G_A, __BA },
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{ R___, _G__, __B_, ___A, RG__, ____, ____, ____ },
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{ RGB_, RG_A, R_BA, _GBA, RGBA, ____, ____, ____ }
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};
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@ -209,9 +209,16 @@ namespace Ryujinx.Graphics.Gal.Shader
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int LutIndex;
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LutIndex = GetOperGpr0(OpCode).Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
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LutIndex = GetOperGpr0 (OpCode).Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
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LutIndex |= GetOperGpr28(OpCode).Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
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if (LutIndex == 0)
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{
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//Both registers are RZ, color is not written anywhere.
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//So, the intruction is basically a no-op.
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return;
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}
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int ChMask = MaskLut[LutIndex, (OpCode >> 50) & 7];
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for (int Ch = 0; Ch < 4; Ch++)
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@ -227,6 +234,26 @@ namespace Ryujinx.Graphics.Gal.Shader
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int RegInc = 0;
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ShaderIrOperGpr GetDst()
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{
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ShaderIrOperGpr Dst;
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switch (LutIndex)
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{
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case 1: Dst = GetOperGpr0 (OpCode); break;
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case 2: Dst = GetOperGpr28(OpCode); break;
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case 3: Dst = (RegInc >> 1) != 0
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? GetOperGpr28(OpCode)
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: GetOperGpr0 (OpCode); break;
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default: throw new InvalidOperationException();
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}
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Dst.Index += RegInc++ & 1;
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return Dst;
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}
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for (int Ch = 0; Ch < 4; Ch++)
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{
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if (!IsChannelUsed(ChMask, Ch))
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@ -236,18 +263,12 @@ namespace Ryujinx.Graphics.Gal.Shader
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrOperGpr Dst = (RegInc >> 1) != 0
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? GetOperGpr28(OpCode)
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: GetOperGpr0 (OpCode);
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ShaderIrOperGpr Dst = GetDst();
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Dst.Index += RegInc++ & 1;
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if (Dst.Index >= ShaderIrOperGpr.ZRIndex)
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if (Dst.Index != ShaderIrOperGpr.ZRIndex)
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{
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continue;
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Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode));
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}
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Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode));
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}
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}
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