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Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)

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* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions

* Address PR feedback

* Address PR feedback

* Remove another useless temp var

* nit: Alignment

* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()

* Fix encodings and move flag bit test out of the loop
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gdkchan 2018-07-14 13:13:02 -03:00 • committed by GitHub
parent 2f37583ab3
commit 514218ab98
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9 changed files with 265 additions and 153 deletions
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4
ChocolArm64/Instruction/AInstEmitSimdCvt.cs
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@ -337,7 +337,7 @@ namespace ChocolArm64.Instruction
int FBits = GetFBits(Context);
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Bytes = Op.GetBitsCount() >> 3;
for (int Index = 0; Index < (Bytes >> SizeI); Index++)
{
@ -426,7 +426,7 @@ namespace ChocolArm64.Instruction
int FBits = GetFBits(Context);
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Bytes = Op.GetBitsCount() >> 3;
for (int Index = 0; Index < (Bytes >> SizeI); Index++)
{