Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop
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2f37583ab3
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9 changed files with 265 additions and 153 deletions
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@ -14,9 +14,10 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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Context.EmitLdintzr(Op.Rn);
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@ -42,9 +43,10 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Op.DstIndex, Op.Size);
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@ -64,7 +66,7 @@ namespace ChocolArm64.Instruction
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Position = Op.Imm4;
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@ -329,7 +331,7 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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@ -355,7 +357,7 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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@ -382,7 +384,7 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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