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Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)

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* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdCrypto.cs
This commit is contained in:
LDj3SNuD 2018-08-27 08:44:01 +02:00 • committed by gdkchan
parent 43c4e7c78d
commit 68300368d7
7 changed files with 775 additions and 53 deletions
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6
Ryujinx.Tests/Cpu/CpuTestSimd.cs
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@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu
});
}
[Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
[Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")]
public void Sha256su0_V([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Random(5)] ulong Z0, [Random(5)] ulong Z1,
[Random(5)] ulong A0, [Random(5)] ulong A1)
[Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1,
[Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1)
{
uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);