Mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). (#662)

Browse source 
* Update CpuTestSimdCvt.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdShImm.cs

* Update InstEmitSimdCvt.cs

* Update OpCodeTable.cs

* Update InstEmitSimdCvt.cs
This commit is contained in:
LDj3SNuD 2019-04-21 04:07:35 +02:00 • committed by gdkchan
parent 9e923b1473
commit 74da8785a5
5 changed files with 342 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

106
Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
View file

@ -288,6 +288,42 @@ namespace Ryujinx.Tests.Cpu
};
}
private static uint[] _SU_Cvt_F_Gp_WS_()
{
return new uint[]
{
0x1E220000u, // SCVTF S0, W0
0x1E230000u // UCVTF S0, W0
};
}
private static uint[] _SU_Cvt_F_Gp_WD_()
{
return new uint[]
{
0x1E620000u, // SCVTF D0, W0
0x1E630000u // UCVTF D0, W0
};
}
private static uint[] _SU_Cvt_F_Gp_XS_()
{
return new uint[]
{
0x9E220000u, // SCVTF S0, X0
0x9E230000u // UCVTF S0, X0
};
}
private static uint[] _SU_Cvt_F_Gp_XD_()
{
return new uint[]
{
0x9E620000u, // SCVTF D0, X0
0x9E630000u // UCVTF D0, X0
};
}
private static uint[] _SU_Cvt_F_Gp_Fixed_WS_()
{
return new uint[]
@ -480,6 +516,74 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WS([ValueSource("_SU_Cvt_F_Gp_WS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WD([ValueSource("_SU_Cvt_F_Gp_WD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XS([ValueSource("_SU_Cvt_F_Gp_XS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XD([ValueSource("_SU_Cvt_F_Gp_XD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource("_SU_Cvt_F_Gp_Fixed_WS_")] uint opcodes,
[Values(0u)] uint rd,
@ -561,7 +665,7 @@ namespace Ryujinx.Tests.Cpu
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn();
CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
}
#endif
}