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Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)

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* Implement VMOVL and VORR.I32 AArch32 SIMD instructions

* Rename <dt> to <size> on test description

* Rename Widen to Long and improve VMOVL implementation a bit
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gdkchan 2020-03-10 02:17:30 -03:00 • committed by GitHub
parent 08c0e3829b
commit 89ccec197e
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9 changed files with 165 additions and 7 deletions
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30
Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs
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@ -228,6 +228,36 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VMOVL.<size> <Qd>, <Dm>")]
public void Vmovl([Values(0u, 1u, 2u, 3u)] uint vm,
[Values(0u, 2u, 4u, 6u)] uint vd,
[Values(1u, 2u, 4u)] uint imm3H,
[Values] bool u)
{
// This is not VMOVL because imm3H = 0, but once
// we shift in the imm3H value it turns into VMOVL.
uint opcode = 0xf2800a10u; // VMOV.I16 D0, #0
opcode |= (vm & 0x10) << 1;
opcode |= (vm & 0xf);
opcode |= (vd & 0x10) << 18;
opcode |= (vd & 0xf) << 12;
opcode |= (imm3H & 0x7) << 19;
if (u)
{
opcode |= 1 << 24;
}
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VTRN.<size> <Vd>, <Vm>")]
public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm,
[Values(0u, 1u, 2u, 3u)] uint vd,