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Refactoring and optimization on CPU translation (#661)

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* Refactoring and optimization on CPU translation

* Remove now unused property

* Rename ilBlock -> block (local)

* Change equality comparison on RegisterMask for consistency

Co-Authored-By: gdkchan <gab.dark.100@gmail.com>

* Add back the aggressive inlining attribute to the Synchronize method

* Implement IEquatable on the Register struct

* Fix identation
This commit is contained in:
gdkchan 2019-04-26 01:55:12 -03:00 • committed by jduncanator
parent 2b8eac1bce
commit 8a7d99cdea
48 changed files with 1257 additions and 1280 deletions
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29
ChocolArm64/Instructions/InstEmit32Helper.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
@ -31,7 +32,7 @@ namespace ChocolArm64.Instructions
{
if (register == RegisterAlias.Aarch32Pc)
{
context.EmitStoreState();
context.EmitStoreContext();
EmitBxWritePc(context);
}
@ -112,13 +113,13 @@ namespace ChocolArm64.Instructions
switch (mode)
{
case Aarch32Mode.User:
case Aarch32Mode.System: return RegisterAlias.SpUsr;
case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
case Aarch32Mode.System: return RegisterAlias.SpUsr;
case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
default: throw new ArgumentException(nameof(mode));
}
@ -128,12 +129,12 @@ namespace ChocolArm64.Instructions
{
case Aarch32Mode.User:
case Aarch32Mode.Hypervisor:
case Aarch32Mode.System: return RegisterAlias.LrUsr;
case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
case Aarch32Mode.System: return RegisterAlias.LrUsr;
case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
default: throw new ArgumentException(nameof(mode));
}

1
ChocolArm64/Instructions/InstEmitAlu.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;

3
ChocolArm64/Instructions/InstEmitAlu32.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System.Reflection.Emit;
@ -122,7 +123,7 @@ namespace ChocolArm64.Instructions
private static void EmitAluWritePc(ILEmitterCtx context)
{
context.EmitStoreState();
context.EmitStoreContext();
if (IsThumb(context.CurrOp))
{

1
ChocolArm64/Instructions/InstEmitCcmp.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;

1
ChocolArm64/Instructions/InstEmitCsel.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.Translation;
using System.Reflection.Emit;

9
ChocolArm64/Instructions/InstEmitException.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System.Reflection.Emit;
@ -21,7 +22,7 @@ namespace ChocolArm64.Instructions
{
OpCodeException64 op = (OpCodeException64)context.CurrOp;
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdarg(TranslatedSub.StateArgIdx);
@ -48,7 +49,7 @@ namespace ChocolArm64.Instructions
if (context.CurrBlock.Next != null)
{
context.EmitLoadState();
context.EmitLoadContext();
}
else
{
@ -62,7 +63,7 @@ namespace ChocolArm64.Instructions
{
OpCode64 op = context.CurrOp;
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdarg(TranslatedSub.StateArgIdx);
@ -73,7 +74,7 @@ namespace ChocolArm64.Instructions
if (context.CurrBlock.Next != null)
{
context.EmitLoadState();
context.EmitLoadContext();
}
else
{

17
ChocolArm64/Instructions/InstEmitFlow.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System.Reflection.Emit;
@ -19,7 +20,7 @@ namespace ChocolArm64.Instructions
}
else
{
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdc_I8(op.Imm);
context.Emit(OpCodes.Ret);
@ -50,7 +51,7 @@ namespace ChocolArm64.Instructions
context.EmitLdintzr(op.Rn);
context.EmitLdc_I(op.Position + 4);
context.EmitStint(RegisterAlias.Lr);
context.EmitStoreState();
context.EmitStoreContext();
EmitVirtualCall(context);
}
@ -61,7 +62,7 @@ namespace ChocolArm64.Instructions
context.HasIndirectJump = true;
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdintzr(op.Rn);
EmitVirtualJump(context);
@ -82,7 +83,7 @@ namespace ChocolArm64.Instructions
public static void Ret(ILEmitterCtx context)
{
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdint(RegisterAlias.Lr);
context.Emit(OpCodes.Ret);
@ -115,7 +116,7 @@ namespace ChocolArm64.Instructions
if (context.CurrBlock.Next == null)
{
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdc_I8(op.Position + 4);
context.Emit(OpCodes.Ret);
@ -123,7 +124,7 @@ namespace ChocolArm64.Instructions
}
else
{
context.EmitStoreState();
context.EmitStoreContext();
ILLabel lblTaken = new ILLabel();
@ -151,7 +152,7 @@ namespace ChocolArm64.Instructions
if (context.CurrBlock.Next == null)
{
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdc_I8(op.Position + 4);
context.Emit(OpCodes.Ret);
@ -159,7 +160,7 @@ namespace ChocolArm64.Instructions
}
else
{
context.EmitStoreState();
context.EmitStoreContext();
ILLabel lblTaken = new ILLabel();

4
ChocolArm64/Instructions/InstEmitFlow32.cs
View file

@ -19,7 +19,7 @@ namespace ChocolArm64.Instructions
}
else
{
context.EmitStoreState();
context.EmitStoreContext();
context.EmitLdc_I8(op.Imm);
context.Emit(OpCodes.Ret);
@ -40,7 +40,7 @@ namespace ChocolArm64.Instructions
{
IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
context.EmitStoreState();
context.EmitStoreContext();
EmitLoadFromRegister(context, op.Rm);

11
ChocolArm64/Instructions/InstEmitFlowHelper.cs
View file

@ -1,3 +1,4 @@
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System.Reflection;
@ -11,7 +12,7 @@ namespace ChocolArm64.Instructions
{
if (context.Tier == TranslationTier.Tier0)
{
context.EmitStoreState();
context.EmitStoreContext();
context.TranslateAhead(imm);
@ -26,13 +27,13 @@ namespace ChocolArm64.Instructions
{
context.HasSlowCall = true;
context.EmitStoreState();
context.EmitStoreContext();
context.TranslateAhead(imm);
context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitFieldLoad(typeof(CpuThreadState).GetField(nameof(CpuThreadState.CurrentTranslator),
context.EmitLdfld(typeof(CpuThreadState).GetField(nameof(CpuThreadState.CurrentTranslator),
BindingFlags.Instance |
BindingFlags.NonPublic));
@ -72,7 +73,7 @@ namespace ChocolArm64.Instructions
context.EmitSttmp();
context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitFieldLoad(typeof(CpuThreadState).GetField(nameof(CpuThreadState.CurrentTranslator),
context.EmitLdfld(typeof(CpuThreadState).GetField(nameof(CpuThreadState.CurrentTranslator),
BindingFlags.Instance |
BindingFlags.NonPublic));
@ -132,7 +133,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Pop);
context.EmitLoadState();
context.EmitLoadContext();
}
else
{

1
ChocolArm64/Instructions/InstEmitMemory32.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;

1
ChocolArm64/Instructions/InstEmitMemoryEx.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.Memory;
using ChocolArm64.State;
using ChocolArm64.Translation;

1
ChocolArm64/Instructions/InstEmitMemoryHelper.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.Memory;
using ChocolArm64.State;
using ChocolArm64.Translation;

1
ChocolArm64/Instructions/InstEmitSimdArithmetic.cs
View file

@ -2,6 +2,7 @@
// https://www.agner.org/optimize/#vectorclass @ vectori128.h
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;

1
ChocolArm64/Instructions/InstEmitSimdCmp.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;

1
ChocolArm64/Instructions/InstEmitSimdMove.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Decoders;
using ChocolArm64.IntermediateRepresentation;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;