Refactoring and optimization on CPU translation (#661)
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
This commit is contained in:
gdkchan
jduncanator
parent
2b8eac1bce
commit
8a7d99cdea
48 changed files with 1257 additions and 1280 deletions
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@ -1,5 +1,6 @@
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using ChocolArm64.Decoders;
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using ChocolArm64.Instructions;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using System;
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@ -16,16 +17,23 @@ namespace ChocolArm64.Translation
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private TranslatorCache _cache;
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private TranslatorQueue _queue;
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private Dictionary<long, ILLabel> _labels;
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private long _subPosition;
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private int _opcIndex;
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private Block _currBlock;
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public Block CurrBlock => _currBlock;
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public OpCode64 CurrOp => _currBlock?.OpCodes[_opcIndex];
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public Block CurrBlock
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{
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get
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{
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return _currBlock;
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}
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set
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{
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_currBlock = value;
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ResetBlockState();
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}
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}
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public OpCode64 CurrOp { get; set; }
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public TranslationTier Tier { get; }
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@ -35,13 +43,15 @@ namespace ChocolArm64.Translation
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public bool HasSlowCall { get; set; }
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private Dictionary<Block, ILBlock> _visitedBlocks;
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private Dictionary<long, ILLabel> _labels;
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private Queue<Block> _branchTargets;
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private Dictionary<ILLabel, BasicBlock> _irLabels;
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private List<ILBlock> _ilBlocks;
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private List<BasicBlock> _irBlocks;
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private ILBlock _ilBlock;
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private BasicBlock _irBlock;
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private bool _needsNewBlock;
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private OpCode64 _optOpLastCompare;
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private OpCode64 _optOpLastFlagSet;
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@ -72,36 +82,25 @@ namespace ChocolArm64.Translation
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MemoryManager memory,
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TranslatorCache cache,
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TranslatorQueue queue,
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TranslationTier tier,
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Block graph)
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TranslationTier tier)
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{
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Memory = memory ?? throw new ArgumentNullException(nameof(memory));
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_cache = cache ?? throw new ArgumentNullException(nameof(cache));
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_queue = queue ?? throw new ArgumentNullException(nameof(queue));
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_currBlock = graph ?? throw new ArgumentNullException(nameof(graph));
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Memory = memory ?? throw new ArgumentNullException(nameof(memory));
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_cache = cache ?? throw new ArgumentNullException(nameof(cache));
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_queue = queue ?? throw new ArgumentNullException(nameof(queue));
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Tier = tier;
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_labels = new Dictionary<long, ILLabel>();
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_visitedBlocks = new Dictionary<Block, ILBlock>();
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_irLabels = new Dictionary<ILLabel, BasicBlock>();
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_visitedBlocks.Add(graph, new ILBlock());
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_irBlocks = new List<BasicBlock>();
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_branchTargets = new Queue<Block>();
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NewNextBlock();
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_ilBlocks = new List<ILBlock>();
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EmitSynchronization();
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_subPosition = graph.Position;
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ResetBlockState();
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if (AdvanceOpCode())
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{
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EmitSynchronization();
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_ilBlock.Add(new ILOpCodeLoadState(_ilBlock, isSubEntry: true));
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}
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EmitLoadContext();
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}
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public static int GetIntTempIndex()
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@ -114,96 +113,15 @@ namespace ChocolArm64.Translation
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return UserVecTempStart + _userVecTempCount++;
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}
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public ILBlock[] GetILBlocks()
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public BasicBlock[] GetBlocks()
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{
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EmitAllOpCodes();
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return _ilBlocks.ToArray();
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return _irBlocks.ToArray();
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}
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private void EmitAllOpCodes()
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{
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do
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{
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EmitOpCode();
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}
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while (AdvanceOpCode());
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}
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private void EmitOpCode()
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{
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if (_currBlock == null)
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{
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return;
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}
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int opcIndex = _opcIndex;
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if (opcIndex == 0)
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{
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MarkLabel(GetLabel(_currBlock.Position));
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}
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bool isLastOp = opcIndex == CurrBlock.OpCodes.Count - 1;
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if (isLastOp && CurrBlock.Branch != null &&
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(ulong)CurrBlock.Branch.Position <= (ulong)CurrBlock.Position)
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{
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EmitSynchronization();
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}
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//On AARCH32 mode, (almost) all instruction can be conditionally
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//executed, and the required condition is encoded on the opcode.
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//We handle that here, skipping the instruction if the condition
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//is not met. We can just ignore it when the condition is "Always",
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//because in this case the instruction is always going to be executed.
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//Condition "Never" is also ignored because this is a special encoding
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//used by some unconditional instructions.
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ILLabel lblSkip = null;
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if (CurrOp is OpCode32 op && op.Cond < Condition.Al)
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{
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lblSkip = new ILLabel();
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EmitCondBranch(lblSkip, GetInverseCond(op.Cond));
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}
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CurrOp.Emitter(this);
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if (lblSkip != null)
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{
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MarkLabel(lblSkip);
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//If this is the last op on the block, and there's no "next" block
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//after this one, then we have to return right now, with the address
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//of the next instruction to be executed (in the case that the condition
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//is false, and the branch was not taken, as all basic blocks should end with
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//some kind of branch).
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if (isLastOp && CurrBlock.Next == null)
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{
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EmitStoreState();
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EmitLdc_I8(CurrOp.Position + CurrOp.OpCodeSizeInBytes);
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Emit(OpCodes.Ret);
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}
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}
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_ilBlock.Add(new ILBarrier());
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}
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private static Condition GetInverseCond(Condition cond)
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{
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//Bit 0 of all conditions is basically a negation bit, so
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//inverting this bit has the effect of inverting the condition.
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return (Condition)((int)cond ^ 1);
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}
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private void EmitSynchronization()
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public void EmitSynchronization()
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{
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EmitLdarg(TranslatedSub.StateArgIdx);
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EmitLdc_I4(_currBlock.OpCodes.Count);
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EmitPrivateCall(typeof(CpuThreadState), nameof(CpuThreadState.Synchronize));
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EmitLdc_I4(0);
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@ -219,83 +137,24 @@ namespace ChocolArm64.Translation
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MarkLabel(lblContinue);
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}
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private bool AdvanceOpCode()
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public void ResetBlockStateForPredicatedOp()
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{
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if (_currBlock == null)
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//Check if this is a predicated instruction that modifies flags,
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//in this case the value of the flags is unknown as we don't know
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//in advance if the instruction is going to be executed or not.
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//So, we reset the block state to prevent an invalid optimization.
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if (CurrOp == _optOpLastFlagSet)
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{
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return false;
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}
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while (++_opcIndex >= _currBlock.OpCodes.Count)
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{
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if (!AdvanceBlock())
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{
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return false;
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}
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ResetBlockState();
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}
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return true;
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}
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private bool AdvanceBlock()
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{
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if (_currBlock.Branch != null)
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{
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if (_visitedBlocks.TryAdd(_currBlock.Branch, _ilBlock.Branch))
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{
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_branchTargets.Enqueue(_currBlock.Branch);
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}
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}
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if (_currBlock.Next != null)
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{
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if (_visitedBlocks.TryAdd(_currBlock.Next, _ilBlock.Next))
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{
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_currBlock = _currBlock.Next;
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return true;
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}
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else
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{
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Emit(OpCodes.Br, GetLabel(_currBlock.Next.Position));
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}
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}
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return _branchTargets.TryDequeue(out _currBlock);
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}
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private void ResetBlockState()
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{
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_ilBlock = _visitedBlocks[_currBlock];
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_ilBlocks.Add(_ilBlock);
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_ilBlock.Next = GetOrCreateILBlock(_currBlock.Next);
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_ilBlock.Branch = GetOrCreateILBlock(_currBlock.Branch);
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_opcIndex = -1;
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_optOpLastFlagSet = null;
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_optOpLastCompare = null;
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}
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private ILBlock GetOrCreateILBlock(Block block)
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{
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if (block == null)
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{
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return null;
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}
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if (_visitedBlocks.TryGetValue(block, out ILBlock ilBlock))
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{
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return ilBlock;
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}
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return new ILBlock();
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}
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public void TranslateAhead(long position, ExecutionMode mode = ExecutionMode.Aarch64)
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{
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if (_cache.TryGetSubroutine(position, out TranslatedSub sub) && sub.Tier != TranslationTier.Tier0)
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@ -320,19 +179,12 @@ namespace ChocolArm64.Translation
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return false;
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}
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if (!_cache.TryGetSubroutine(op.Imm, out TranslatedSub sub))
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if (!_cache.TryGetSubroutine(op.Imm, out TranslatedSub sub) || sub.Tier != TranslationTier.Tier0)
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{
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return false;
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}
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//It's not worth to call a Tier0 method, because
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//it contains slow code, rather than the entire function.
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if (sub.Tier == TranslationTier.Tier0)
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{
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return false;
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}
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EmitStoreState(sub);
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EmitStoreContext();
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for (int index = 0; index < TranslatedSub.FixedArgTypes.Length; index++)
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{
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@ -350,8 +202,8 @@ namespace ChocolArm64.Translation
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InstEmitAluHelper.EmitAluLoadOpers(this);
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Stloc(CmpOptTmp2Index, VarType.Int);
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Stloc(CmpOptTmp1Index, VarType.Int);
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Stloc(CmpOptTmp2Index, RegisterType.Int);
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Stloc(CmpOptTmp1Index, RegisterType.Int);
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}
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private Dictionary<Condition, OpCode> _branchOps = new Dictionary<Condition, OpCode>()
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@ -375,8 +227,8 @@ namespace ChocolArm64.Translation
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{
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if (_optOpLastCompare.Emitter == InstEmit.Subs)
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{
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Ldloc(CmpOptTmp1Index, VarType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp2Index, VarType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp1Index, RegisterType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp2Index, RegisterType.Int, _optOpLastCompare.RegisterSize);
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Emit(_branchOps[cond], target);
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@ -388,17 +240,17 @@ namespace ChocolArm64.Translation
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&& cond != Condition.LeUn)
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{
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//There are several limitations that needs to be taken into account for CMN comparisons:
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//* The unsigned comparisons are not valid, as they depend on the
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//- The unsigned comparisons are not valid, as they depend on the
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//carry flag value, and they will have different values for addition and
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//subtraction. For addition, it's carry, and for subtraction, it's borrow.
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//So, we need to make sure we're not doing a unsigned compare for the CMN case.
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//* We can only do the optimization for the immediate variants,
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//- We can only do the optimization for the immediate variants,
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//because when the second operand value is exactly INT_MIN, we can't
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//negate the value as theres no positive counterpart.
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//Such invalid values can't be encoded on the immediate encodings.
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if (_optOpLastCompare is IOpCodeAluImm64 op)
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{
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Ldloc(CmpOptTmp1Index, VarType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp1Index, RegisterType.Int, _optOpLastCompare.RegisterSize);
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if (_optOpLastCompare.RegisterSize == RegisterSize.Int32)
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{
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@ -456,9 +308,7 @@ namespace ChocolArm64.Translation
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break;
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}
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ilOp = (intCond & 1) != 0
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? OpCodes.Brfalse
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: OpCodes.Brtrue;
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ilOp = (intCond & 1) != 0 ? OpCodes.Brfalse : OpCodes.Brtrue;
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}
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else
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{
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@ -484,17 +334,14 @@ namespace ChocolArm64.Translation
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bool sz64 = CurrOp.RegisterSize != RegisterSize.Int32;
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if (sz64 == (intType == IntType.UInt64 ||
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intType == IntType.Int64))
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if (sz64 == (intType == IntType.UInt64 || intType == IntType.Int64))
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{
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return;
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}
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if (sz64)
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{
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Emit(intType >= IntType.Int8
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? OpCodes.Conv_I8
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: OpCodes.Conv_U8);
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Emit(intType >= IntType.Int8 ? OpCodes.Conv_I8 : OpCodes.Conv_U8);
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}
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else
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{
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@ -520,14 +367,14 @@ namespace ChocolArm64.Translation
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{
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if (amount > 0)
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{
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Stloc(RorTmpIndex, VarType.Int);
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Ldloc(RorTmpIndex, VarType.Int);
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Stloc(RorTmpIndex, RegisterType.Int);
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Ldloc(RorTmpIndex, RegisterType.Int);
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EmitLdc_I4(amount);
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Emit(OpCodes.Shr_Un);
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Ldloc(RorTmpIndex, VarType.Int);
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Ldloc(RorTmpIndex, RegisterType.Int);
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EmitLdc_I4(CurrOp.GetBitsCount() - amount);
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@ -550,32 +397,60 @@ namespace ChocolArm64.Translation
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public void MarkLabel(ILLabel label)
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{
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_ilBlock.Add(label);
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if (_irLabels.TryGetValue(label, out BasicBlock nextBlock))
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{
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nextBlock.Index = _irBlocks.Count;
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_irBlocks.Add(nextBlock);
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NextBlock(nextBlock);
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}
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else
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{
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NewNextBlock();
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_irLabels.Add(label, _irBlock);
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}
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AddOperation(Operation.MarkLabel(label));
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}
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public void Emit(OpCode ilOp)
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{
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_ilBlock.Add(new ILOpCode(ilOp));
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AddOperation(Operation.IL(ilOp));
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if (ilOp == OpCodes.Ret)
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{
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NextBlock(null);
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|
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_needsNewBlock = true;
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}
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}
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public void Emit(OpCode ilOp, ILLabel label)
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{
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_ilBlock.Add(new ILOpCodeBranch(ilOp, label));
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AddOperation(Operation.ILBranch(ilOp, label));
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_needsNewBlock = true;
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|
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if (!_irLabels.TryGetValue(label, out BasicBlock branchBlock))
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{
|
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branchBlock = new BasicBlock();
|
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|
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_irLabels.Add(label, branchBlock);
|
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}
|
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|
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_irBlock.Branch = branchBlock;
|
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}
|
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|
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public void EmitFieldLoad(FieldInfo info)
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public void EmitLdfld(FieldInfo info)
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{
|
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_ilBlock.Add(new ILOpCodeLoadField(info));
|
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}
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public void EmitPrint(string text)
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{
|
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_ilBlock.Add(new ILOpCodeLog(text));
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AddOperation(Operation.LoadField(info));
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}
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public void EmitLdarg(int index)
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{
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_ilBlock.Add(new ILOpCodeLoad(index, VarType.Arg));
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AddOperation(Operation.LoadArgument(index));
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}
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public void EmitLdintzr(int index)
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|
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@ -602,24 +477,16 @@ namespace ChocolArm64.Translation
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}
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}
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|
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public void EmitLoadState()
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public void EmitLoadContext()
|
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{
|
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if (_ilBlock.Next == null)
|
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{
|
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throw new InvalidOperationException("Can't load state for next block, because there's no next block.");
|
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}
|
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_needsNewBlock = true;
|
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|
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_ilBlock.Add(new ILOpCodeLoadState(_ilBlock.Next));
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AddOperation(Operation.LoadContext());
|
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}
|
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public void EmitStoreState()
|
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public void EmitStoreContext()
|
||||
{
|
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_ilBlock.Add(new ILOpCodeStoreState(_ilBlock));
|
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}
|
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|
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private void EmitStoreState(TranslatedSub callSub)
|
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{
|
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_ilBlock.Add(new ILOpCodeStoreState(_ilBlock, callSub));
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AddOperation(Operation.StoreContext());
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}
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public void EmitLdtmp() => EmitLdint(IntGpTmp1Index);
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@ -637,17 +504,17 @@ namespace ChocolArm64.Translation
|
|||
public void EmitLdvectmp3() => EmitLdvec(VecGpTmp3Index);
|
||||
public void EmitStvectmp3() => EmitStvec(VecGpTmp3Index);
|
||||
|
||||
public void EmitLdint(int index) => Ldloc(index, VarType.Int);
|
||||
public void EmitStint(int index) => Stloc(index, VarType.Int);
|
||||
public void EmitLdint(int index) => Ldloc(index, RegisterType.Int);
|
||||
public void EmitStint(int index) => Stloc(index, RegisterType.Int);
|
||||
|
||||
public void EmitLdvec(int index) => Ldloc(index, VarType.Vector);
|
||||
public void EmitStvec(int index) => Stloc(index, VarType.Vector);
|
||||
public void EmitLdvec(int index) => Ldloc(index, RegisterType.Vector);
|
||||
public void EmitStvec(int index) => Stloc(index, RegisterType.Vector);
|
||||
|
||||
public void EmitLdflg(int index) => Ldloc(index, VarType.Flag);
|
||||
public void EmitLdflg(int index) => Ldloc(index, RegisterType.Flag);
|
||||
public void EmitStflg(int index)
|
||||
{
|
||||
//Set this only if any of the NZCV flag bits were modified.
|
||||
//This is used to ensure that, when emiting a direct IL branch
|
||||
//This is used to ensure that when emiting a direct IL branch
|
||||
//instruction for compare + branch sequences, we're not expecting
|
||||
//to use comparison values from an old instruction, when in fact
|
||||
//the flags were already overwritten by another instruction further along.
|
||||
|
|
@ -656,22 +523,22 @@ namespace ChocolArm64.Translation
|
|||
_optOpLastFlagSet = CurrOp;
|
||||
}
|
||||
|
||||
Stloc(index, VarType.Flag);
|
||||
Stloc(index, RegisterType.Flag);
|
||||
}
|
||||
|
||||
private void Ldloc(int index, VarType varType)
|
||||
private void Ldloc(int index, RegisterType type)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeLoad(index, varType, CurrOp.RegisterSize));
|
||||
AddOperation(Operation.LoadLocal(index, type, CurrOp.RegisterSize));
|
||||
}
|
||||
|
||||
private void Ldloc(int index, VarType varType, RegisterSize registerSize)
|
||||
private void Ldloc(int index, RegisterType type, RegisterSize size)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeLoad(index, varType, registerSize));
|
||||
AddOperation(Operation.LoadLocal(index, type, size));
|
||||
}
|
||||
|
||||
private void Stloc(int index, VarType varType)
|
||||
private void Stloc(int index, RegisterType type)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeStore(index, varType, CurrOp.RegisterSize));
|
||||
AddOperation(Operation.StoreLocal(index, type, CurrOp.RegisterSize));
|
||||
}
|
||||
|
||||
public void EmitCallPropGet(Type objType, string propName)
|
||||
|
|
@ -726,7 +593,19 @@ namespace ChocolArm64.Translation
|
|||
|
||||
public void EmitCall(MethodInfo mthdInfo, bool isVirtual = false)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeCall(mthdInfo ?? throw new ArgumentNullException(nameof(mthdInfo)), isVirtual));
|
||||
if (mthdInfo == null)
|
||||
{
|
||||
throw new ArgumentNullException(nameof(mthdInfo));
|
||||
}
|
||||
|
||||
if (isVirtual)
|
||||
{
|
||||
AddOperation(Operation.CallVirtual(mthdInfo));
|
||||
}
|
||||
else
|
||||
{
|
||||
AddOperation(Operation.Call(mthdInfo));
|
||||
}
|
||||
}
|
||||
|
||||
public void EmitLdc_I(long value)
|
||||
|
|
@ -743,22 +622,22 @@ namespace ChocolArm64.Translation
|
|||
|
||||
public void EmitLdc_I4(int value)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeConst(value));
|
||||
AddOperation(Operation.LoadConstant(value));
|
||||
}
|
||||
|
||||
public void EmitLdc_I8(long value)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeConst(value));
|
||||
AddOperation(Operation.LoadConstant(value));
|
||||
}
|
||||
|
||||
public void EmitLdc_R4(float value)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeConst(value));
|
||||
AddOperation(Operation.LoadConstant(value));
|
||||
}
|
||||
|
||||
public void EmitLdc_R8(double value)
|
||||
{
|
||||
_ilBlock.Add(new ILOpCodeConst(value));
|
||||
AddOperation(Operation.LoadConstant(value));
|
||||
}
|
||||
|
||||
public void EmitZnFlagCheck()
|
||||
|
|
@ -781,5 +660,50 @@ namespace ChocolArm64.Translation
|
|||
|
||||
EmitStflg(flag);
|
||||
}
|
||||
|
||||
private void AddOperation(Operation operation)
|
||||
{
|
||||
if (_needsNewBlock)
|
||||
{
|
||||
NewNextBlock();
|
||||
}
|
||||
|
||||
_irBlock.Add(operation);
|
||||
}
|
||||
|
||||
private void NewNextBlock()
|
||||
{
|
||||
BasicBlock block = new BasicBlock(_irBlocks.Count);
|
||||
|
||||
_irBlocks.Add(block);
|
||||
|
||||
NextBlock(block);
|
||||
}
|
||||
|
||||
private void NextBlock(BasicBlock nextBlock)
|
||||
{
|
||||
if (_irBlock != null && !EndsWithUnconditional(_irBlock))
|
||||
{
|
||||
_irBlock.Next = nextBlock;
|
||||
}
|
||||
|
||||
_irBlock = nextBlock;
|
||||
|
||||
_needsNewBlock = false;
|
||||
}
|
||||
|
||||
private static bool EndsWithUnconditional(BasicBlock block)
|
||||
{
|
||||
Operation lastOp = block.GetLastOp();
|
||||
|
||||
if (lastOp == null || lastOp.Type != OperationType.ILBranch)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
OpCode opCode = lastOp.GetArg<OpCode>(0);
|
||||
|
||||
return opCode == OpCodes.Br || opCode == OpCodes.Br_S;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue