Separate GPU engines and make state follow official docs (part 1/2) (#2422)
* Use DeviceState for compute and i2m * Migrate 2D class, more comments * Migrate DMA copy engine * Remove now unused code * Replace GpuState by GpuAccessorState on GpuAcessor, since compute no longer has a GpuState * More comments * Add logging (disabled) * Add back i2m on 3D engine
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gdkchan
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30 changed files with 2599 additions and 460 deletions
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using Ryujinx.Common;
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using Ryujinx.Graphics.Device;
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using Ryujinx.Graphics.Texture;
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using System;
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using System.Collections.Generic;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Graphics.Gpu.Engine.InlineToMemory
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{
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/// <summary>
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/// Represents a Inline-to-Memory engine class.
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/// </summary>
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class InlineToMemoryClass : IDeviceState
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{
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private readonly GpuContext _context;
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private readonly GpuChannel _channel;
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private readonly DeviceState<InlineToMemoryClassState> _state;
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private bool _isLinear;
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private int _offset;
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private int _size;
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private ulong _dstGpuVa;
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private int _dstX;
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private int _dstY;
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private int _dstWidth;
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private int _dstHeight;
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private int _dstStride;
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private int _dstGobBlocksInY;
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private int _lineLengthIn;
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private int _lineCount;
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private bool _finished;
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private int[] _buffer;
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/// <summary>
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/// Creates a new instance of the Inline-to-Memory engine class.
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/// </summary>
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/// <param name="context">GPU context</param>
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/// <param name="channel">GPU channel</param>
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/// <param name="initializeState">Indicates if the internal state should be initialized. Set to false if part of another engine</param>
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protected InlineToMemoryClass(GpuContext context, GpuChannel channel, bool initializeState)
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{
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_context = context;
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_channel = channel;
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if (initializeState)
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{
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_state = new DeviceState<InlineToMemoryClassState>(new Dictionary<string, RwCallback>
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{
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{ nameof(InlineToMemoryClassState.LaunchDma), new RwCallback(LaunchDma, null) },
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{ nameof(InlineToMemoryClassState.LoadInlineData), new RwCallback(LoadInlineData, null) }
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});
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}
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}
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/// <summary>
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/// Creates a new instance of the inline-to-memory engine class.
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/// </summary>
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/// <param name="context">GPU context</param>
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/// <param name="channel">GPU channel</param>
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public InlineToMemoryClass(GpuContext context, GpuChannel channel) : this(context, channel, true)
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{
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}
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/// <summary>
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/// Reads data from the class registers.
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/// </summary>
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/// <param name="offset">Register byte offset</param>
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/// <returns>Data at the specified offset</returns>
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public virtual int Read(int offset) => _state.Read(offset);
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/// <summary>
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/// Writes data to the class registers.
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/// </summary>
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/// <param name="offset">Register byte offset</param>
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/// <param name="data">Data to be written</param>
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public virtual void Write(int offset, int data) => _state.Write(offset, data);
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/// <summary>
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/// Launches Inline-to-Memory engine DMA copy.
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/// </summary>
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/// <param name="argument">Method call argument</param>
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protected virtual void LaunchDma(int argument)
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{
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LaunchDma(ref _state.State, argument);
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}
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/// <summary>
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/// Launches Inline-to-Memory engine DMA copy.
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/// </summary>
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/// <param name="state">Current class state</param>
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/// <param name="argument">Method call argument</param>
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protected void LaunchDma(ref InlineToMemoryClassState state, int argument)
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{
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_isLinear = (argument & 1) != 0;
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_offset = 0;
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_size = (int)(state.LineLengthIn * state.LineCount);
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int count = BitUtils.DivRoundUp(_size, 4);
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if (_buffer == null || _buffer.Length < count)
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{
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_buffer = new int[count];
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}
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ulong dstGpuVa = ((ulong)state.OffsetOutUpperValue << 32) | state.OffsetOut;
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ulong dstBaseAddress = _channel.MemoryManager.Translate(dstGpuVa);
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// Trigger read tracking, to flush any managed resources in the destination region.
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_channel.MemoryManager.Physical.GetSpan(dstBaseAddress, _size, true);
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_dstGpuVa = dstGpuVa;
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_dstX = state.SetDstOriginBytesXV;
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_dstY = state.SetDstOriginSamplesYV;
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_dstWidth = (int)state.SetDstWidth;
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_dstHeight = (int)state.SetDstHeight;
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_dstStride = (int)state.PitchOut;
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_dstGobBlocksInY = 1 << (int)state.SetDstBlockSizeHeight;
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_lineLengthIn = (int)state.LineLengthIn;
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_lineCount = (int)state.LineCount;
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_finished = false;
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}
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/// <summary>
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/// Pushes a word of data to the Inline-to-Memory engine.
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/// </summary>
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/// <param name="argument">Method call argument</param>
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protected void LoadInlineData(int argument)
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{
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if (!_finished)
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{
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_buffer[_offset++] = argument;
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if (_offset * 4 >= _size)
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{
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FinishTransfer();
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}
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}
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}
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/// <summary>
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/// Performs actual copy of the inline data after the transfer is finished.
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/// </summary>
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private void FinishTransfer()
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{
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Span<byte> data = MemoryMarshal.Cast<int, byte>(_buffer).Slice(0, _size);
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if (_isLinear && _lineCount == 1)
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{
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ulong address = _channel.MemoryManager.Translate(_dstGpuVa);
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_channel.MemoryManager.Physical.Write(address, data);
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}
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else
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{
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var dstCalculator = new OffsetCalculator(
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_dstWidth,
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_dstHeight,
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_dstStride,
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_isLinear,
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_dstGobBlocksInY,
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1);
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int srcOffset = 0;
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ulong dstBaseAddress = _channel.MemoryManager.Translate(_dstGpuVa);
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for (int y = _dstY; y < _dstY + _lineCount; y++)
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{
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int x1 = _dstX;
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int x2 = _dstX + _lineLengthIn;
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int x2Trunc = _dstX + BitUtils.AlignDown(_lineLengthIn, 16);
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int x;
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for (x = x1; x < x2Trunc; x += 16, srcOffset += 16)
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{
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int dstOffset = dstCalculator.GetOffset(x, y);
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ulong dstAddress = dstBaseAddress + (ulong)dstOffset;
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Span<byte> pixel = data.Slice(srcOffset, 16);
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_channel.MemoryManager.Physical.Write(dstAddress, pixel);
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}
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for (; x < x2; x++, srcOffset++)
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{
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int dstOffset = dstCalculator.GetOffset(x, y);
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ulong dstAddress = dstBaseAddress + (ulong)dstOffset;
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Span<byte> pixel = data.Slice(srcOffset, 1);
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_channel.MemoryManager.Physical.Write(dstAddress, pixel);
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}
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}
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}
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_finished = true;
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_context.AdvanceSequence();
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}
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}
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}
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@ -0,0 +1,181 @@
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// This file was auto-generated from NVIDIA official Maxwell definitions.
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namespace Ryujinx.Graphics.Gpu.Engine.InlineToMemory
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{
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/// <summary>
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/// Notify type.
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/// </summary>
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enum NotifyType
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{
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WriteOnly = 0,
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WriteThenAwaken = 1,
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}
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/// <summary>
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/// Width in GOBs of the destination texture.
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/// </summary>
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enum SetDstBlockSizeWidth
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{
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OneGob = 0,
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}
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/// <summary>
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/// Height in GOBs of the destination texture.
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/// </summary>
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enum SetDstBlockSizeHeight
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{
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OneGob = 0,
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TwoGobs = 1,
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FourGobs = 2,
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EightGobs = 3,
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SixteenGobs = 4,
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ThirtytwoGobs = 5,
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}
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/// <summary>
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/// Depth in GOBs of the destination texture.
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/// </summary>
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enum SetDstBlockSizeDepth
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{
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OneGob = 0,
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TwoGobs = 1,
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FourGobs = 2,
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EightGobs = 3,
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SixteenGobs = 4,
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ThirtytwoGobs = 5,
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}
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/// <summary>
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/// Memory layout of the destination texture.
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/// </summary>
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enum LaunchDmaDstMemoryLayout
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{
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Blocklinear = 0,
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Pitch = 1,
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}
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/// <summary>
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/// DMA completion type.
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/// </summary>
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enum LaunchDmaCompletionType
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{
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FlushDisable = 0,
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FlushOnly = 1,
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ReleaseSemaphore = 2,
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}
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/// <summary>
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/// DMA interrupt type.
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/// </summary>
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enum LaunchDmaInterruptType
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{
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None = 0,
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Interrupt = 1,
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}
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/// <summary>
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/// DMA semaphore structure size.
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/// </summary>
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enum LaunchDmaSemaphoreStructSize
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{
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FourWords = 0,
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OneWord = 1,
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}
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/// <summary>
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/// DMA semaphore reduction operation.
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/// </summary>
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enum LaunchDmaReductionOp
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{
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RedAdd = 0,
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RedMin = 1,
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RedMax = 2,
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RedInc = 3,
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RedDec = 4,
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RedAnd = 5,
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RedOr = 6,
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RedXor = 7,
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}
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/// <summary>
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/// DMA semaphore reduction format.
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/// </summary>
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enum LaunchDmaReductionFormat
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{
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Unsigned32 = 0,
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Signed32 = 1,
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}
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/// <summary>
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/// Inline-to-Memory class state.
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/// </summary>
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unsafe struct InlineToMemoryClassState
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{
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#pragma warning disable CS0649
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public uint SetObject;
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public int SetObjectClassId => (int)((SetObject >> 0) & 0xFFFF);
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public int SetObjectEngineId => (int)((SetObject >> 16) & 0x1F);
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public fixed uint Reserved04[63];
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public uint NoOperation;
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public uint SetNotifyA;
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public int SetNotifyAAddressUpper => (int)((SetNotifyA >> 0) & 0xFF);
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public uint SetNotifyB;
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public uint Notify;
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public NotifyType NotifyType => (NotifyType)(Notify);
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public uint WaitForIdle;
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public fixed uint Reserved114[7];
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public uint SetGlobalRenderEnableA;
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public int SetGlobalRenderEnableAOffsetUpper => (int)((SetGlobalRenderEnableA >> 0) & 0xFF);
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public uint SetGlobalRenderEnableB;
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public uint SetGlobalRenderEnableC;
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public int SetGlobalRenderEnableCMode => (int)((SetGlobalRenderEnableC >> 0) & 0x7);
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public uint SendGoIdle;
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public uint PmTrigger;
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public uint PmTriggerWfi;
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public fixed uint Reserved148[2];
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public uint SetInstrumentationMethodHeader;
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public uint SetInstrumentationMethodData;
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public fixed uint Reserved158[10];
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public uint LineLengthIn;
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public uint LineCount;
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public uint OffsetOutUpper;
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public int OffsetOutUpperValue => (int)((OffsetOutUpper >> 0) & 0xFF);
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public uint OffsetOut;
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public uint PitchOut;
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public uint SetDstBlockSize;
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public SetDstBlockSizeWidth SetDstBlockSizeWidth => (SetDstBlockSizeWidth)((SetDstBlockSize >> 0) & 0xF);
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public SetDstBlockSizeHeight SetDstBlockSizeHeight => (SetDstBlockSizeHeight)((SetDstBlockSize >> 4) & 0xF);
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public SetDstBlockSizeDepth SetDstBlockSizeDepth => (SetDstBlockSizeDepth)((SetDstBlockSize >> 8) & 0xF);
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public uint SetDstWidth;
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public uint SetDstHeight;
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public uint SetDstDepth;
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public uint SetDstLayer;
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public uint SetDstOriginBytesX;
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public int SetDstOriginBytesXV => (int)((SetDstOriginBytesX >> 0) & 0xFFFFF);
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public uint SetDstOriginSamplesY;
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public int SetDstOriginSamplesYV => (int)((SetDstOriginSamplesY >> 0) & 0xFFFF);
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public uint LaunchDma;
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public LaunchDmaDstMemoryLayout LaunchDmaDstMemoryLayout => (LaunchDmaDstMemoryLayout)((LaunchDma >> 0) & 0x1);
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public LaunchDmaCompletionType LaunchDmaCompletionType => (LaunchDmaCompletionType)((LaunchDma >> 4) & 0x3);
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public LaunchDmaInterruptType LaunchDmaInterruptType => (LaunchDmaInterruptType)((LaunchDma >> 8) & 0x3);
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public LaunchDmaSemaphoreStructSize LaunchDmaSemaphoreStructSize => (LaunchDmaSemaphoreStructSize)((LaunchDma >> 12) & 0x1);
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public bool LaunchDmaReductionEnable => (LaunchDma & 0x2) != 0;
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public LaunchDmaReductionOp LaunchDmaReductionOp => (LaunchDmaReductionOp)((LaunchDma >> 13) & 0x7);
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public LaunchDmaReductionFormat LaunchDmaReductionFormat => (LaunchDmaReductionFormat)((LaunchDma >> 2) & 0x3);
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public bool LaunchDmaSysmembarDisable => (LaunchDma & 0x40) != 0;
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public uint LoadInlineData;
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public fixed uint Reserved1B8[9];
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public uint SetI2mSemaphoreA;
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public int SetI2mSemaphoreAOffsetUpper => (int)((SetI2mSemaphoreA >> 0) & 0xFF);
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public uint SetI2mSemaphoreB;
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public uint SetI2mSemaphoreC;
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public fixed uint Reserved1E8[2];
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public uint SetI2mSpareNoop00;
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public uint SetI2mSpareNoop01;
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public uint SetI2mSpareNoop02;
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public uint SetI2mSpareNoop03;
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public fixed uint Reserved200[3200];
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public MmeShadowScratch SetMmeShadowScratch;
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#pragma warning restore CS0649
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}
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}
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