Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
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e174100474
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20 changed files with 217 additions and 93 deletions
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@ -4,11 +4,13 @@ namespace ChocolArm64.Translation
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{
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class AILBlock : IAILEmit
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{
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntAwOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecAwOutputs { get; private set; }
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public bool HasStateStore { get; private set; }
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@ -24,13 +26,22 @@ namespace ChocolArm64.Translation
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public void Add(IAILEmit ILEmitter)
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{
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if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
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if (ILEmitter is AILBarrier)
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{
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//Those barriers are used to separate the groups of CIL
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//opcodes emitted by each ARM instruction.
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//We can only consider the new outputs for doing input elimination
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//after all the CIL opcodes used by the instruction being emitted.
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IntAwOutputs = IntOutputs;
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VecAwOutputs = VecOutputs;
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}
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else if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
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{
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switch (Ld.IoType)
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{
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case AIoType.Flag: IntInputs |= ((1L << Ld.Index) << 32) & ~IntOutputs; break;
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case AIoType.Int: IntInputs |= (1L << Ld.Index) & ~IntOutputs; break;
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case AIoType.Vector: VecInputs |= (1L << Ld.Index) & ~VecOutputs; break;
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case AIoType.Flag: IntInputs |= ((1L << Ld.Index) << 32) & ~IntAwOutputs; break;
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case AIoType.Int: IntInputs |= (1L << Ld.Index) & ~IntAwOutputs; break;
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case AIoType.Vector: VecInputs |= (1L << Ld.Index) & ~VecAwOutputs; break;
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}
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}
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else if (ILEmitter is AILOpCodeStore St)
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