[Ryujinx.Graphics.Shader] Address dotnet-format issues (#5373)
* dotnet format style --severity info Some changes were manually reverted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Silence dotnet format IDE0059 warnings * Address or silence dotnet format CA1069 warnings * Address or silence dotnet format CA2211 warnings * Address review comments * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Run dotnet format whitespace after rebase * Run dotnet format style after rebase * Run dotnet format whitespace after rebase * Run dotnet format style after rebase * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Fix naming rule violation, Convert shader properties to auto-property and convert values to const * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Run dotnet format after rebase * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Run dotnet format after rebase * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Fix naming rule violations * Add trailing commas * Remove unused members and most unnecessary value assignments * Remove more unnecessary assignments * Remove NRE suppressor
This commit is contained in:
parent
e055217292
commit
9becbd7d72
162 changed files with 1611 additions and 1627 deletions
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@ -1,7 +1,6 @@
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using System.Collections.Generic;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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@ -21,10 +20,10 @@ namespace Ryujinx.Graphics.Shader.Instructions
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Tessellation = TessellationControl | TessellationEvaluation,
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VertexTessellationGeometry = Vertex | Tessellation | Geometry,
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TessellationGeometryFragment = Tessellation | Geometry | Fragment,
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AllGraphics = Vertex | Tessellation | Geometry | Fragment
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AllGraphics = Vertex | Tessellation | Geometry | Fragment,
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}
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private struct AttributeEntry
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private readonly struct AttributeEntry
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{
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public int BaseOffset { get; }
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public AggregateType Type { get; }
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@ -344,8 +343,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
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AggregateType.Vector2 => 2,
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AggregateType.Vector3 => 3,
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AggregateType.Vector4 => 4,
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_ => 1
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_ => 1,
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};
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}
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}
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}
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}
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@ -7,352 +7,352 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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public static void AtomCas(EmitterContext context)
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{
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InstAtomCas op = context.GetOp<InstAtomCas>();
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context.GetOp<InstAtomCas>();
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context.Config.GpuAccessor.Log("Shader instruction AtomCas is not implemented.");
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}
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public static void AtomsCas(EmitterContext context)
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{
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InstAtomsCas op = context.GetOp<InstAtomsCas>();
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context.GetOp<InstAtomsCas>();
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context.Config.GpuAccessor.Log("Shader instruction AtomsCas is not implemented.");
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}
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public static void B2r(EmitterContext context)
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{
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InstB2r op = context.GetOp<InstB2r>();
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context.GetOp<InstB2r>();
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context.Config.GpuAccessor.Log("Shader instruction B2r is not implemented.");
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}
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public static void Bpt(EmitterContext context)
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{
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InstBpt op = context.GetOp<InstBpt>();
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context.GetOp<InstBpt>();
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context.Config.GpuAccessor.Log("Shader instruction Bpt is not implemented.");
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}
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public static void Cctl(EmitterContext context)
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{
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InstCctl op = context.GetOp<InstCctl>();
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context.GetOp<InstCctl>();
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context.Config.GpuAccessor.Log("Shader instruction Cctl is not implemented.");
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}
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public static void Cctll(EmitterContext context)
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{
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InstCctll op = context.GetOp<InstCctll>();
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context.GetOp<InstCctll>();
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context.Config.GpuAccessor.Log("Shader instruction Cctll is not implemented.");
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}
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public static void Cctlt(EmitterContext context)
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{
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InstCctlt op = context.GetOp<InstCctlt>();
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context.GetOp<InstCctlt>();
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context.Config.GpuAccessor.Log("Shader instruction Cctlt is not implemented.");
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}
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public static void Cs2r(EmitterContext context)
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{
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InstCs2r op = context.GetOp<InstCs2r>();
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context.GetOp<InstCs2r>();
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context.Config.GpuAccessor.Log("Shader instruction Cs2r is not implemented.");
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}
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public static void FchkR(EmitterContext context)
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{
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InstFchkR op = context.GetOp<InstFchkR>();
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context.GetOp<InstFchkR>();
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context.Config.GpuAccessor.Log("Shader instruction FchkR is not implemented.");
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}
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public static void FchkI(EmitterContext context)
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{
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InstFchkI op = context.GetOp<InstFchkI>();
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context.GetOp<InstFchkI>();
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context.Config.GpuAccessor.Log("Shader instruction FchkI is not implemented.");
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}
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public static void FchkC(EmitterContext context)
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{
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InstFchkC op = context.GetOp<InstFchkC>();
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context.GetOp<InstFchkC>();
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context.Config.GpuAccessor.Log("Shader instruction FchkC is not implemented.");
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}
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public static void Getcrsptr(EmitterContext context)
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{
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InstGetcrsptr op = context.GetOp<InstGetcrsptr>();
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context.GetOp<InstGetcrsptr>();
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context.Config.GpuAccessor.Log("Shader instruction Getcrsptr is not implemented.");
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}
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public static void Getlmembase(EmitterContext context)
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{
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InstGetlmembase op = context.GetOp<InstGetlmembase>();
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context.GetOp<InstGetlmembase>();
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context.Config.GpuAccessor.Log("Shader instruction Getlmembase is not implemented.");
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}
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public static void Ide(EmitterContext context)
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{
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InstIde op = context.GetOp<InstIde>();
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context.GetOp<InstIde>();
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context.Config.GpuAccessor.Log("Shader instruction Ide is not implemented.");
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}
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public static void IdpR(EmitterContext context)
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{
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InstIdpR op = context.GetOp<InstIdpR>();
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context.GetOp<InstIdpR>();
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context.Config.GpuAccessor.Log("Shader instruction IdpR is not implemented.");
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}
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public static void IdpC(EmitterContext context)
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{
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InstIdpC op = context.GetOp<InstIdpC>();
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context.GetOp<InstIdpC>();
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context.Config.GpuAccessor.Log("Shader instruction IdpC is not implemented.");
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}
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public static void ImadspR(EmitterContext context)
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{
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InstImadspR op = context.GetOp<InstImadspR>();
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context.GetOp<InstImadspR>();
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context.Config.GpuAccessor.Log("Shader instruction ImadspR is not implemented.");
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}
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public static void ImadspI(EmitterContext context)
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{
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InstImadspI op = context.GetOp<InstImadspI>();
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context.GetOp<InstImadspI>();
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context.Config.GpuAccessor.Log("Shader instruction ImadspI is not implemented.");
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}
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public static void ImadspC(EmitterContext context)
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{
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InstImadspC op = context.GetOp<InstImadspC>();
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context.GetOp<InstImadspC>();
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context.Config.GpuAccessor.Log("Shader instruction ImadspC is not implemented.");
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}
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public static void ImadspRc(EmitterContext context)
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{
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InstImadspRc op = context.GetOp<InstImadspRc>();
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context.GetOp<InstImadspRc>();
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context.Config.GpuAccessor.Log("Shader instruction ImadspRc is not implemented.");
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}
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public static void Jcal(EmitterContext context)
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{
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InstJcal op = context.GetOp<InstJcal>();
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context.GetOp<InstJcal>();
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context.Config.GpuAccessor.Log("Shader instruction Jcal is not implemented.");
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}
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public static void Jmp(EmitterContext context)
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{
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InstJmp op = context.GetOp<InstJmp>();
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context.GetOp<InstJmp>();
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context.Config.GpuAccessor.Log("Shader instruction Jmp is not implemented.");
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}
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public static void Jmx(EmitterContext context)
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{
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InstJmx op = context.GetOp<InstJmx>();
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context.GetOp<InstJmx>();
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context.Config.GpuAccessor.Log("Shader instruction Jmx is not implemented.");
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}
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public static void Ld(EmitterContext context)
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{
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InstLd op = context.GetOp<InstLd>();
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context.GetOp<InstLd>();
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context.Config.GpuAccessor.Log("Shader instruction Ld is not implemented.");
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}
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public static void Lepc(EmitterContext context)
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{
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InstLepc op = context.GetOp<InstLepc>();
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context.GetOp<InstLepc>();
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context.Config.GpuAccessor.Log("Shader instruction Lepc is not implemented.");
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}
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public static void Longjmp(EmitterContext context)
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{
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InstLongjmp op = context.GetOp<InstLongjmp>();
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context.GetOp<InstLongjmp>();
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context.Config.GpuAccessor.Log("Shader instruction Longjmp is not implemented.");
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}
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public static void Pexit(EmitterContext context)
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{
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InstPexit op = context.GetOp<InstPexit>();
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context.GetOp<InstPexit>();
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context.Config.GpuAccessor.Log("Shader instruction Pexit is not implemented.");
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}
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public static void Pixld(EmitterContext context)
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{
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InstPixld op = context.GetOp<InstPixld>();
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context.GetOp<InstPixld>();
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context.Config.GpuAccessor.Log("Shader instruction Pixld is not implemented.");
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}
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public static void Plongjmp(EmitterContext context)
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{
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InstPlongjmp op = context.GetOp<InstPlongjmp>();
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context.GetOp<InstPlongjmp>();
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context.Config.GpuAccessor.Log("Shader instruction Plongjmp is not implemented.");
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}
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public static void Pret(EmitterContext context)
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{
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InstPret op = context.GetOp<InstPret>();
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context.GetOp<InstPret>();
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context.Config.GpuAccessor.Log("Shader instruction Pret is not implemented.");
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}
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public static void PrmtR(EmitterContext context)
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{
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InstPrmtR op = context.GetOp<InstPrmtR>();
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context.GetOp<InstPrmtR>();
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context.Config.GpuAccessor.Log("Shader instruction PrmtR is not implemented.");
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}
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public static void PrmtI(EmitterContext context)
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{
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InstPrmtI op = context.GetOp<InstPrmtI>();
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context.GetOp<InstPrmtI>();
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context.Config.GpuAccessor.Log("Shader instruction PrmtI is not implemented.");
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}
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public static void PrmtC(EmitterContext context)
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{
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InstPrmtC op = context.GetOp<InstPrmtC>();
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context.GetOp<InstPrmtC>();
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context.Config.GpuAccessor.Log("Shader instruction PrmtC is not implemented.");
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}
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public static void PrmtRc(EmitterContext context)
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{
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InstPrmtRc op = context.GetOp<InstPrmtRc>();
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context.GetOp<InstPrmtRc>();
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context.Config.GpuAccessor.Log("Shader instruction PrmtRc is not implemented.");
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}
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public static void R2b(EmitterContext context)
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{
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InstR2b op = context.GetOp<InstR2b>();
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context.GetOp<InstR2b>();
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context.Config.GpuAccessor.Log("Shader instruction R2b is not implemented.");
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}
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public static void Ram(EmitterContext context)
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{
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InstRam op = context.GetOp<InstRam>();
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context.GetOp<InstRam>();
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context.Config.GpuAccessor.Log("Shader instruction Ram is not implemented.");
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}
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public static void Rtt(EmitterContext context)
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{
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InstRtt op = context.GetOp<InstRtt>();
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context.GetOp<InstRtt>();
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context.Config.GpuAccessor.Log("Shader instruction Rtt is not implemented.");
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}
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public static void Sam(EmitterContext context)
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{
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InstSam op = context.GetOp<InstSam>();
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context.GetOp<InstSam>();
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context.Config.GpuAccessor.Log("Shader instruction Sam is not implemented.");
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}
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public static void Setcrsptr(EmitterContext context)
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{
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InstSetcrsptr op = context.GetOp<InstSetcrsptr>();
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context.GetOp<InstSetcrsptr>();
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context.Config.GpuAccessor.Log("Shader instruction Setcrsptr is not implemented.");
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}
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public static void Setlmembase(EmitterContext context)
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{
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InstSetlmembase op = context.GetOp<InstSetlmembase>();
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context.GetOp<InstSetlmembase>();
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context.Config.GpuAccessor.Log("Shader instruction Setlmembase is not implemented.");
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}
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public static void St(EmitterContext context)
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{
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InstSt op = context.GetOp<InstSt>();
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context.GetOp<InstSt>();
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context.Config.GpuAccessor.Log("Shader instruction St is not implemented.");
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}
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public static void Stp(EmitterContext context)
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{
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InstStp op = context.GetOp<InstStp>();
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context.GetOp<InstStp>();
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context.Config.GpuAccessor.Log("Shader instruction Stp is not implemented.");
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}
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public static void Txa(EmitterContext context)
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{
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InstTxa op = context.GetOp<InstTxa>();
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context.GetOp<InstTxa>();
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context.Config.GpuAccessor.Log("Shader instruction Txa is not implemented.");
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}
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public static void Vabsdiff(EmitterContext context)
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{
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InstVabsdiff op = context.GetOp<InstVabsdiff>();
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context.GetOp<InstVabsdiff>();
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context.Config.GpuAccessor.Log("Shader instruction Vabsdiff is not implemented.");
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}
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public static void Vabsdiff4(EmitterContext context)
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{
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InstVabsdiff4 op = context.GetOp<InstVabsdiff4>();
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context.GetOp<InstVabsdiff4>();
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context.Config.GpuAccessor.Log("Shader instruction Vabsdiff4 is not implemented.");
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}
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public static void Vadd(EmitterContext context)
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{
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InstVadd op = context.GetOp<InstVadd>();
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context.GetOp<InstVadd>();
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context.Config.GpuAccessor.Log("Shader instruction Vadd is not implemented.");
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}
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public static void Votevtg(EmitterContext context)
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{
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InstVotevtg op = context.GetOp<InstVotevtg>();
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context.GetOp<InstVotevtg>();
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context.Config.GpuAccessor.Log("Shader instruction Votevtg is not implemented.");
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}
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public static void Vset(EmitterContext context)
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{
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InstVset op = context.GetOp<InstVset>();
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context.GetOp<InstVset>();
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context.Config.GpuAccessor.Log("Shader instruction Vset is not implemented.");
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}
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public static void Vshl(EmitterContext context)
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{
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InstVshl op = context.GetOp<InstVshl>();
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context.GetOp<InstVshl>();
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context.Config.GpuAccessor.Log("Shader instruction Vshl is not implemented.");
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}
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public static void Vshr(EmitterContext context)
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{
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InstVshr op = context.GetOp<InstVshr>();
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context.GetOp<InstVshr>();
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context.Config.GpuAccessor.Log("Shader instruction Vshr is not implemented.");
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}
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}
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}
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}
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@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using System;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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@ -18,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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IDstFmt.S16 => short.MinValue,
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IDstFmt.U32 => uint.MinValue,
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IDstFmt.S32 => int.MinValue,
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_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
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_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
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||||
};
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}
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@ -30,7 +29,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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IDstFmt.S16 => short.MaxValue,
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IDstFmt.U32 => uint.MaxValue,
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IDstFmt.S32 => int.MaxValue,
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_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
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||||
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
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||||
};
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||||
}
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@ -44,7 +43,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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ISrcDstFmt.S16 => short.MinValue,
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ISrcDstFmt.U32 => uint.MinValue,
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ISrcDstFmt.S32 => int.MinValue,
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_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
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_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
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};
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}
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@ -58,7 +57,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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ISrcDstFmt.S16 => short.MaxValue,
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ISrcDstFmt.U32 => uint.MaxValue,
|
||||
ISrcDstFmt.S32 => int.MaxValue,
|
||||
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
|
||||
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -69,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
BoolOp.And => context.BitwiseAnd(input, pred),
|
||||
BoolOp.Or => context.BitwiseOr(input, pred),
|
||||
BoolOp.Xor => context.BitwiseExclusiveOr(input, pred),
|
||||
_ => input
|
||||
_ => input,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -89,7 +88,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
VectorSelect.S8B3 => SignExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
|
||||
VectorSelect.S16H0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
|
||||
VectorSelect.S16H1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
|
||||
_ => src
|
||||
_ => src,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -134,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
|
||||
context.Copy(GetZF(), context.FPCompareEqual(dest, zero, fpType));
|
||||
context.Copy(GetNF(), context.FPCompareLess (dest, zero, fpType));
|
||||
context.Copy(GetNF(), context.FPCompareLess(dest, zero, fpType));
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -157,4 +156,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return result;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -33,7 +33,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
for (int index = 0; index < (int)op.AlSize + 1; index++)
|
||||
{
|
||||
Register rd = new Register(op.Dest + index, RegisterType.Gpr);
|
||||
Register rd = new(op.Dest + index, RegisterType.Gpr);
|
||||
|
||||
if (rd.IsRZ)
|
||||
{
|
||||
|
@ -91,7 +91,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
break;
|
||||
}
|
||||
|
||||
Register rd = new Register(op.SrcB + index, RegisterType.Gpr);
|
||||
Register rd = new(op.SrcB + index, RegisterType.Gpr);
|
||||
|
||||
if (op.Phys)
|
||||
{
|
||||
|
@ -380,4 +380,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -22,7 +22,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static void Depbar(EmitterContext context)
|
||||
{
|
||||
#pragma warning disable IDE0059 // Remove unnecessary value assignment
|
||||
InstDepbar op = context.GetOp<InstDepbar>();
|
||||
#pragma warning restore IDE0059
|
||||
|
||||
// No operation.
|
||||
}
|
||||
|
@ -41,4 +43,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -191,4 +191,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(GetDest(rd), res);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
using Ryujinx.Graphics.Shader.Decoders;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -80,8 +79,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
Ccc.Oft => GetVF(),
|
||||
Ccc.Rle => context.BitwiseOr(GetNF(), GetZF()),
|
||||
Ccc.Rgt => context.BitwiseNot(context.BitwiseOr(GetNF(), GetZF())),
|
||||
_ => Const(defaultCond)
|
||||
_ => Const(defaultCond),
|
||||
};
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
|
|||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -140,7 +139,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
IntegerRound.Floor => context.FPFloor(srcB, srcType.ToInstFPType()),
|
||||
IntegerRound.Ceil => context.FPCeiling(srcB, srcType.ToInstFPType()),
|
||||
IntegerRound.Trunc => context.FPTruncate(srcB, srcType.ToInstFPType()),
|
||||
_ => srcB
|
||||
_ => srcB,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -191,7 +190,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
RoundMode2.Floor => context.FPFloor(srcB, fpType),
|
||||
RoundMode2.Ceil => context.FPCeiling(srcB, fpType),
|
||||
RoundMode2.Trunc => context.FPTruncate(srcB, fpType),
|
||||
_ => srcB
|
||||
_ => srcB,
|
||||
};
|
||||
|
||||
if (!isSignedInt)
|
||||
|
@ -422,4 +421,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return type == DstFmt.F64 ? Instruction.FP64 : Instruction.FP32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
using Ryujinx.Graphics.Shader.Decoders;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -458,7 +457,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
MultiplyScale.M2 => ConstF(2f),
|
||||
MultiplyScale.M4 => ConstF(4f),
|
||||
MultiplyScale.M8 => ConstF(8f),
|
||||
_ => ConstF(1f) // Invalid, behave as if it had no scale.
|
||||
_ => ConstF(1f), // Invalid, behave as if it had no scale.
|
||||
};
|
||||
|
||||
if (scaleConst.AsFloat() == 1f)
|
||||
|
@ -529,4 +528,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(GetDest(rd), GetHalfPacked(context, swizzle, res, rd));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
|
|||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -484,8 +483,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
else
|
||||
{
|
||||
Operand low = context.BitwiseAnd(res[0], Const(0xffff));
|
||||
Operand high = context.ShiftLeft (res[1], Const(16));
|
||||
Operand low = context.BitwiseAnd(res[0], Const(0xffff));
|
||||
Operand high = context.ShiftLeft(res[1], Const(16));
|
||||
|
||||
Operand packed = context.BitwiseOr(low, high);
|
||||
|
||||
|
@ -546,20 +545,16 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
else
|
||||
{
|
||||
Instruction inst;
|
||||
|
||||
switch (cond & ~FComp.Nan)
|
||||
var inst = (cond & ~FComp.Nan) switch
|
||||
{
|
||||
case FComp.Lt: inst = Instruction.CompareLess; break;
|
||||
case FComp.Eq: inst = Instruction.CompareEqual; break;
|
||||
case FComp.Le: inst = Instruction.CompareLessOrEqual; break;
|
||||
case FComp.Gt: inst = Instruction.CompareGreater; break;
|
||||
case FComp.Ne: inst = Instruction.CompareNotEqual; break;
|
||||
case FComp.Ge: inst = Instruction.CompareGreaterOrEqual; break;
|
||||
|
||||
default: throw new ArgumentException($"Unexpected condition \"{cond}\".");
|
||||
}
|
||||
|
||||
FComp.Lt => Instruction.CompareLess,
|
||||
FComp.Eq => Instruction.CompareEqual,
|
||||
FComp.Le => Instruction.CompareLessOrEqual,
|
||||
FComp.Gt => Instruction.CompareGreater,
|
||||
FComp.Ne => Instruction.CompareNotEqual,
|
||||
FComp.Ge => Instruction.CompareGreaterOrEqual,
|
||||
_ => throw new ArgumentException($"Unexpected condition \"{cond}\"."),
|
||||
};
|
||||
res = context.Add(inst | fpType, Local(), srcA, srcB);
|
||||
|
||||
if ((cond & FComp.Nan) != 0)
|
||||
|
@ -572,4 +567,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return res;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -103,4 +103,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SetFPZnFlags(context, res, writeCC, fpType);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -3,8 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
|||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System.Collections.Generic;
|
||||
using System.Linq;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
namespace Ryujinx.Graphics.Shader.Instructions
|
||||
|
@ -13,14 +11,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
public static void Bra(EmitterContext context)
|
||||
{
|
||||
InstBra op = context.GetOp<InstBra>();
|
||||
context.GetOp<InstBra>();
|
||||
|
||||
EmitBranch(context, context.CurrBlock.Successors[^1].Address);
|
||||
}
|
||||
|
||||
public static void Brk(EmitterContext context)
|
||||
{
|
||||
InstBrk op = context.GetOp<InstBrk>();
|
||||
context.GetOp<InstBrk>();
|
||||
|
||||
EmitBrkContSync(context);
|
||||
}
|
||||
|
@ -123,7 +121,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static void Cal(EmitterContext context)
|
||||
{
|
||||
InstCal op = context.GetOp<InstCal>();
|
||||
context.GetOp<InstCal>();
|
||||
|
||||
DecodedFunction function = context.Program.GetFunctionByAddress(context.CurrOp.GetAbsoluteAddress());
|
||||
|
||||
|
@ -147,7 +145,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static void Cont(EmitterContext context)
|
||||
{
|
||||
InstCont op = context.GetOp<InstCont>();
|
||||
context.GetOp<InstCont>();
|
||||
|
||||
EmitBrkContSync(context);
|
||||
}
|
||||
|
@ -185,28 +183,28 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static void Kil(EmitterContext context)
|
||||
{
|
||||
InstKil op = context.GetOp<InstKil>();
|
||||
context.GetOp<InstKil>();
|
||||
|
||||
context.Discard();
|
||||
}
|
||||
|
||||
public static void Pbk(EmitterContext context)
|
||||
{
|
||||
InstPbk op = context.GetOp<InstPbk>();
|
||||
context.GetOp<InstPbk>();
|
||||
|
||||
EmitPbkPcntSsy(context);
|
||||
}
|
||||
|
||||
public static void Pcnt(EmitterContext context)
|
||||
{
|
||||
InstPcnt op = context.GetOp<InstPcnt>();
|
||||
context.GetOp<InstPcnt>();
|
||||
|
||||
EmitPbkPcntSsy(context);
|
||||
}
|
||||
|
||||
public static void Ret(EmitterContext context)
|
||||
{
|
||||
InstRet op = context.GetOp<InstRet>();
|
||||
context.GetOp<InstRet>();
|
||||
|
||||
if (context.IsNonMain)
|
||||
{
|
||||
|
@ -220,14 +218,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static void Ssy(EmitterContext context)
|
||||
{
|
||||
InstSsy op = context.GetOp<InstSsy>();
|
||||
context.GetOp<InstSsy>();
|
||||
|
||||
EmitPbkPcntSsy(context);
|
||||
}
|
||||
|
||||
public static void Sync(EmitterContext context)
|
||||
{
|
||||
InstSync op = context.GetOp<InstSync>();
|
||||
context.GetOp<InstSync>();
|
||||
|
||||
EmitBrkContSync(context);
|
||||
}
|
||||
|
@ -275,7 +273,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
private static void EmitBranch(EmitterContext context, ulong address)
|
||||
{
|
||||
InstOp op = context.CurrOp;
|
||||
InstConditional opCond = new InstConditional(op.RawOpCode);
|
||||
InstConditional opCond = new(op.RawOpCode);
|
||||
|
||||
// If we're branching to the next instruction, then the branch
|
||||
// is useless and we can ignore it.
|
||||
|
@ -321,4 +319,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
|||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System;
|
||||
using System.Runtime.CompilerServices;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
namespace Ryujinx.Graphics.Shader.Instructions
|
||||
|
@ -111,7 +110,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return new Operand[]
|
||||
{
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref low)),
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref high))
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref high)),
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -123,7 +122,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return new Operand[]
|
||||
{
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref low)),
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref high))
|
||||
ConstF((float)Unsafe.As<ushort, Half>(ref high)),
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -139,56 +138,51 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
public static Operand[] GetHalfUnpacked(EmitterContext context, Operand src, HalfSwizzle swizzle)
|
||||
{
|
||||
switch (swizzle)
|
||||
return swizzle switch
|
||||
{
|
||||
case HalfSwizzle.F16:
|
||||
return new Operand[]
|
||||
{
|
||||
HalfSwizzle.F16 => new Operand[]
|
||||
{
|
||||
context.UnpackHalf2x16Low (src),
|
||||
context.UnpackHalf2x16High(src)
|
||||
};
|
||||
|
||||
case HalfSwizzle.F32: return new Operand[] { src, src };
|
||||
|
||||
case HalfSwizzle.H0H0:
|
||||
return new Operand[]
|
||||
context.UnpackHalf2x16High(src),
|
||||
},
|
||||
HalfSwizzle.F32 => new Operand[] { src, src },
|
||||
HalfSwizzle.H0H0 => new Operand[]
|
||||
{
|
||||
context.UnpackHalf2x16Low(src),
|
||||
context.UnpackHalf2x16Low(src)
|
||||
};
|
||||
|
||||
case HalfSwizzle.H1H1:
|
||||
return new Operand[]
|
||||
context.UnpackHalf2x16Low(src),
|
||||
},
|
||||
HalfSwizzle.H1H1 => new Operand[]
|
||||
{
|
||||
context.UnpackHalf2x16High(src),
|
||||
context.UnpackHalf2x16High(src)
|
||||
};
|
||||
}
|
||||
|
||||
throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
|
||||
context.UnpackHalf2x16High(src),
|
||||
},
|
||||
_ => throw new ArgumentException($"Invalid swizzle \"{swizzle}\"."),
|
||||
};
|
||||
}
|
||||
|
||||
public static Operand GetHalfPacked(EmitterContext context, OFmt swizzle, Operand[] results, int rd)
|
||||
{
|
||||
switch (swizzle)
|
||||
{
|
||||
case OFmt.F16: return context.PackHalf2x16(results[0], results[1]);
|
||||
case OFmt.F16:
|
||||
return context.PackHalf2x16(results[0], results[1]);
|
||||
|
||||
case OFmt.F32: return results[0];
|
||||
case OFmt.F32:
|
||||
return results[0];
|
||||
|
||||
case OFmt.MrgH0:
|
||||
{
|
||||
Operand h1 = GetHalfDest(context, rd, isHigh: true);
|
||||
{
|
||||
Operand h1 = GetHalfDest(context, rd, isHigh: true);
|
||||
|
||||
return context.PackHalf2x16(results[0], h1);
|
||||
}
|
||||
return context.PackHalf2x16(results[0], h1);
|
||||
}
|
||||
|
||||
case OFmt.MrgH1:
|
||||
{
|
||||
Operand h0 = GetHalfDest(context, rd, isHigh: false);
|
||||
{
|
||||
Operand h0 = GetHalfDest(context, rd, isHigh: false);
|
||||
|
||||
return context.PackHalf2x16(h0, results[1]);
|
||||
}
|
||||
return context.PackHalf2x16(h0, results[1]);
|
||||
}
|
||||
}
|
||||
|
||||
throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
|
||||
|
@ -263,4 +257,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return context.BitwiseAnd(src, Const(mask));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -510,7 +510,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
aLow = context.BitwiseNot(aLow);
|
||||
aHigh = context.BitwiseNot(aHigh);
|
||||
|
||||
#pragma warning disable IDE0059 // Remove unnecessary value assignment
|
||||
aLow = AddWithCarry(context, aLow, Const(1), out Operand aLowCOut);
|
||||
#pragma warning restore IDE0059
|
||||
aHigh = context.IAdd(aHigh, aLowCOut);
|
||||
}
|
||||
|
||||
|
@ -696,4 +698,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SetZnFlags(context, res, setCC: true, extended: extended);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
|
|||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -220,7 +219,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
else
|
||||
{
|
||||
res = context.ISubtract(srcA, srcB);
|
||||
#pragma warning disable IDE0059 // Remove unnecessary value assignment
|
||||
res = context.IAdd(res, context.BitwiseNot(GetCF()));
|
||||
#pragma warning restore IDE0059
|
||||
|
||||
switch (cond)
|
||||
{
|
||||
|
@ -287,17 +288,25 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
IComp.Gt => Instruction.CompareGreaterU32,
|
||||
IComp.Ne => Instruction.CompareNotEqual,
|
||||
IComp.Ge => Instruction.CompareGreaterOrEqualU32,
|
||||
_ => throw new InvalidOperationException($"Unexpected condition \"{cond}\".")
|
||||
_ => throw new InvalidOperationException($"Unexpected condition \"{cond}\"."),
|
||||
};
|
||||
|
||||
if (isSigned)
|
||||
{
|
||||
switch (cond)
|
||||
{
|
||||
case IComp.Lt: inst = Instruction.CompareLess; break;
|
||||
case IComp.Le: inst = Instruction.CompareLessOrEqual; break;
|
||||
case IComp.Gt: inst = Instruction.CompareGreater; break;
|
||||
case IComp.Ge: inst = Instruction.CompareGreaterOrEqual; break;
|
||||
case IComp.Lt:
|
||||
inst = Instruction.CompareLess;
|
||||
break;
|
||||
case IComp.Le:
|
||||
inst = Instruction.CompareLessOrEqual;
|
||||
break;
|
||||
case IComp.Gt:
|
||||
inst = Instruction.CompareGreater;
|
||||
break;
|
||||
case IComp.Ge:
|
||||
inst = Instruction.CompareGreaterOrEqual;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -307,4 +316,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return res;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
using Ryujinx.Graphics.Shader.Decoders;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
@ -103,10 +102,10 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
Operand res = logicOp switch
|
||||
{
|
||||
LogicOp.And => res = context.BitwiseAnd(srcA, srcB),
|
||||
LogicOp.Or => res = context.BitwiseOr(srcA, srcB),
|
||||
LogicOp.Xor => res = context.BitwiseExclusiveOr(srcA, srcB),
|
||||
_ => srcB
|
||||
LogicOp.And => context.BitwiseAnd(srcA, srcB),
|
||||
LogicOp.Or => context.BitwiseOr(srcA, srcB),
|
||||
LogicOp.Xor => context.BitwiseExclusiveOr(srcA, srcB),
|
||||
_ => srcB,
|
||||
};
|
||||
|
||||
EmitLopPredWrite(context, res, predOp, destPred);
|
||||
|
@ -164,4 +163,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -68,4 +68,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
// TODO: X flags.
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
|
|||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
using System.Numerics;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
|
@ -48,7 +47,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
AtomsSize.S32 => AtomSize.S32,
|
||||
AtomsSize.U64 => AtomSize.U64,
|
||||
AtomsSize.S64 => AtomSize.S64,
|
||||
_ => AtomSize.U32
|
||||
_ => AtomSize.U32,
|
||||
};
|
||||
|
||||
Operand id = Const(context.Config.ResourceManager.SharedMemoryId);
|
||||
|
@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
for (int index = 0; index < count; index++)
|
||||
{
|
||||
Register dest = new Register(op.Dest + index, RegisterType.Gpr);
|
||||
Register dest = new(op.Dest + index, RegisterType.Gpr);
|
||||
|
||||
if (dest.IsRZ)
|
||||
{
|
||||
|
@ -309,14 +308,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
LsSize2.B64 => 2,
|
||||
LsSize2.B128 => 4,
|
||||
_ => 1
|
||||
_ => 1,
|
||||
};
|
||||
|
||||
Operand baseOffset = context.Copy(srcA);
|
||||
|
||||
for (int index = 0; index < count; index++)
|
||||
{
|
||||
Register dest = new Register(rd + index, RegisterType.Gpr);
|
||||
Register dest = new(rd + index, RegisterType.Gpr);
|
||||
|
||||
if (dest.IsRZ)
|
||||
{
|
||||
|
@ -354,7 +353,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
for (int index = 0; index < count; index++)
|
||||
{
|
||||
Register dest = new Register(rd + index, RegisterType.Gpr);
|
||||
Register dest = new(rd + index, RegisterType.Gpr);
|
||||
|
||||
if (dest.IsRZ)
|
||||
{
|
||||
|
@ -390,7 +389,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
LsSize2.B64 => 2,
|
||||
LsSize2.B128 => 4,
|
||||
_ => 1
|
||||
_ => 1,
|
||||
};
|
||||
|
||||
Operand baseOffset = context.Copy(srcA);
|
||||
|
@ -476,22 +475,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
LsSize.S8 => StorageKind.GlobalMemoryS8,
|
||||
LsSize.U16 => StorageKind.GlobalMemoryU16,
|
||||
LsSize.S16 => StorageKind.GlobalMemoryS16,
|
||||
_ => StorageKind.GlobalMemory
|
||||
_ => StorageKind.GlobalMemory,
|
||||
};
|
||||
}
|
||||
|
||||
private static int GetVectorCount(LsSize size)
|
||||
{
|
||||
switch (size)
|
||||
return size switch
|
||||
{
|
||||
case LsSize.B64:
|
||||
return 2;
|
||||
case LsSize.B128:
|
||||
case LsSize.UB128:
|
||||
return 4;
|
||||
}
|
||||
|
||||
return 1;
|
||||
LsSize.B64 => 2,
|
||||
LsSize.B128 or LsSize.UB128 => 4,
|
||||
_ => 1,
|
||||
};
|
||||
}
|
||||
|
||||
private static (Operand, Operand) Get40BitsAddress(
|
||||
|
@ -544,10 +539,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
switch (size)
|
||||
{
|
||||
case LsSize.U8: value = ZeroExtendTo32(context, value, 8); break;
|
||||
case LsSize.U16: value = ZeroExtendTo32(context, value, 16); break;
|
||||
case LsSize.S8: value = SignExtendTo32(context, value, 8); break;
|
||||
case LsSize.S16: value = SignExtendTo32(context, value, 16); break;
|
||||
case LsSize.U8:
|
||||
value = ZeroExtendTo32(context, value, 8);
|
||||
break;
|
||||
case LsSize.U16:
|
||||
value = ZeroExtendTo32(context, value, 16);
|
||||
break;
|
||||
case LsSize.S8:
|
||||
value = SignExtendTo32(context, value, 8);
|
||||
break;
|
||||
case LsSize.S16:
|
||||
value = SignExtendTo32(context, value, 16);
|
||||
break;
|
||||
}
|
||||
|
||||
return value;
|
||||
|
@ -578,4 +581,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return value;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -212,7 +212,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
int count = ccpr ? RegisterConsts.FlagsCount : RegisterConsts.PredsCount;
|
||||
RegisterType type = ccpr ? RegisterType.Flag : RegisterType.Predicate;
|
||||
int shift = (int)byteSel * 8;
|
||||
|
||||
|
||||
for (int bit = 0; bit < count; bit++)
|
||||
{
|
||||
Operand flag = Register(bit, type);
|
||||
|
@ -228,4 +228,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(GetDest(rd), res);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -94,4 +94,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(GetDest(rd), srcB);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -7,9 +7,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
public static void Nop(EmitterContext context)
|
||||
{
|
||||
InstNop op = context.GetOp<InstNop>();
|
||||
context.GetOp<InstNop>();
|
||||
|
||||
// No operation.
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -113,4 +113,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(dest, res);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -246,4 +246,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(GetDest(rd), res);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation;
|
|||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Numerics;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
|
@ -221,7 +220,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
Operand destOperand = dest != RegisterConsts.RegisterZeroIndex ? Register(dest, RegisterType.Gpr) : null;
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -325,7 +324,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return context.Copy(Register(srcA++, RegisterType.Gpr));
|
||||
}
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -445,10 +444,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
switch (size)
|
||||
{
|
||||
case SuSize.U8: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8)); break;
|
||||
case SuSize.U16: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16)); break;
|
||||
case SuSize.S8: context.Copy(dests[0], SignExtendTo32(context, dests[0], 8)); break;
|
||||
case SuSize.S16: context.Copy(dests[0], SignExtendTo32(context, dests[0], 16)); break;
|
||||
case SuSize.U8:
|
||||
context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8));
|
||||
break;
|
||||
case SuSize.U16:
|
||||
context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16));
|
||||
break;
|
||||
case SuSize.S8:
|
||||
context.Copy(dests[0], SignExtendTo32(context, dests[0], 8));
|
||||
break;
|
||||
case SuSize.S16:
|
||||
context.Copy(dests[0], SignExtendTo32(context, dests[0], 16));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -493,7 +500,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return context.Copy(Register(srcB++, RegisterType.Gpr));
|
||||
}
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -600,7 +607,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return context.Copy(Register(srcB++, RegisterType.Gpr));
|
||||
}
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -699,7 +706,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuatomSize.S64 => 3,
|
||||
SuatomSize.Sd32 => 2,
|
||||
SuatomSize.Sd64 => 3,
|
||||
_ => 2
|
||||
_ => 2,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -715,7 +722,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuatomSize.S64 => TextureFormat.R32G32Uint,
|
||||
SuatomSize.Sd32 => TextureFormat.R32Uint,
|
||||
SuatomSize.Sd64 => TextureFormat.R32G32Uint,
|
||||
_ => TextureFormat.R32Uint
|
||||
_ => TextureFormat.R32Uint,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -732,7 +739,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuatomOp.Or => TextureFlags.BitwiseOr,
|
||||
SuatomOp.Xor => TextureFlags.BitwiseXor,
|
||||
SuatomOp.Exch => TextureFlags.Swap,
|
||||
_ => TextureFlags.Add
|
||||
_ => TextureFlags.Add,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -743,7 +750,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuSize.B64 => 2,
|
||||
SuSize.B128 => 4,
|
||||
SuSize.UB128 => 4,
|
||||
_ => 1
|
||||
_ => 1,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -759,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuSize.B64 => 3,
|
||||
SuSize.B128 => 4,
|
||||
SuSize.UB128 => 4,
|
||||
_ => 2
|
||||
_ => 2,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -775,7 +782,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuSize.B64 => TextureFormat.R32G32Uint,
|
||||
SuSize.B128 => TextureFormat.R32G32B32A32Uint,
|
||||
SuSize.UB128 => TextureFormat.R32G32B32A32Uint,
|
||||
_ => TextureFormat.R32Uint
|
||||
_ => TextureFormat.R32Uint,
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -789,8 +796,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
SuDim._2d => SamplerType.Texture2D,
|
||||
SuDim._2dArray => SamplerType.Texture2D | SamplerType.Array,
|
||||
SuDim._3d => SamplerType.Texture3D,
|
||||
_ => SamplerType.None
|
||||
_ => SamplerType.None,
|
||||
};
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation;
|
|||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Numerics;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
namespace Ryujinx.Graphics.Shader.Instructions
|
||||
|
@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
private static readonly int[,] _maskLut = new int[,]
|
||||
{
|
||||
{ 0b0001, 0b0010, 0b0100, 0b1000, 0b0011, 0b1001, 0b1010, 0b1100 },
|
||||
{ 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }
|
||||
{ 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 },
|
||||
};
|
||||
|
||||
public const bool Sample1DAs2D = true;
|
||||
|
@ -23,7 +22,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
Texs,
|
||||
Tlds,
|
||||
Tld4s
|
||||
Tld4s,
|
||||
}
|
||||
|
||||
public static void Tex(EmitterContext context)
|
||||
|
@ -207,7 +206,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
Operand arrayIndex = isArray ? Ra() : null;
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -353,7 +352,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return;
|
||||
}
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
Operand Ra()
|
||||
{
|
||||
|
@ -722,7 +721,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
Operand arrayIndex = isArray ? Ra() : null;
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
SamplerType type = ConvertSamplerType(dimensions);
|
||||
TextureFlags flags = TextureFlags.Gather;
|
||||
|
@ -864,7 +863,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
TextureFlags flags = TextureFlags.None;
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -996,7 +995,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
|
||||
TextureFlags flags = TextureFlags.Derivatives;
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -1126,7 +1125,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return context.Copy(Register(srcA++, RegisterType.Gpr));
|
||||
}
|
||||
|
||||
List<Operand> sourcesList = new List<Operand>();
|
||||
List<Operand> sourcesList = new();
|
||||
|
||||
if (isBindless)
|
||||
{
|
||||
|
@ -1195,7 +1194,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
TexDim.Array3d => SamplerType.Texture3D | SamplerType.Array,
|
||||
TexDim.Cube => SamplerType.TextureCube,
|
||||
TexDim.ArrayCube => SamplerType.TextureCube | SamplerType.Array,
|
||||
_ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\".")
|
||||
_ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\"."),
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -1309,4 +1308,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return TextureFlags.None;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
using Ryujinx.Graphics.Shader.Decoders;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
|
@ -77,7 +76,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
VideoScale.Shr7 => 7,
|
||||
VideoScale.Shr15 => 15,
|
||||
_ => 0
|
||||
_ => 0,
|
||||
};
|
||||
|
||||
if (shift != 0)
|
||||
|
@ -115,4 +114,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
// TODO: CC.
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -180,4 +180,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
using Ryujinx.Graphics.Shader.Decoders;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
|
@ -39,7 +38,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
ShflMode.Up => context.ShuffleUp(srcA, srcB, srcC),
|
||||
ShflMode.Down => context.ShuffleDown(srcA, srcB, srcC),
|
||||
ShflMode.Bfly => context.ShuffleXor(srcA, srcB, srcC),
|
||||
_ => (null, null)
|
||||
_ => (null, null),
|
||||
};
|
||||
|
||||
context.Copy(GetDest(op.Dest), res);
|
||||
|
@ -81,4 +80,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -3,4 +3,4 @@ using Ryujinx.Graphics.Shader.Translation;
|
|||
namespace Ryujinx.Graphics.Shader.Instructions
|
||||
{
|
||||
delegate void InstEmitter(EmitterContext context);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Translation;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
namespace Ryujinx.Graphics.Shader.Instructions
|
||||
|
@ -9,27 +8,27 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
private enum TruthTable : byte
|
||||
{
|
||||
False = 0x00, // false
|
||||
True = 0xff, // true
|
||||
In = 0xf0, // a
|
||||
And2 = 0xc0, // a & b
|
||||
Or2 = 0xfc, // a | b
|
||||
Xor2 = 0x3c, // a ^ b
|
||||
And3 = 0x80, // a & b & c
|
||||
Or3 = 0xfe, // a | b | c
|
||||
XorAnd = 0x60, // a & (b ^ c)
|
||||
XorOr = 0xf6, // a | (b ^ c)
|
||||
OrAnd = 0xe0, // a & (b | c)
|
||||
AndOr = 0xf8, // a | (b & c)
|
||||
Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true.
|
||||
Majority = 0xe8, // Popcount(a, b, c) >= 2
|
||||
Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off
|
||||
False = 0x00, // false
|
||||
True = 0xff, // true
|
||||
In = 0xf0, // a
|
||||
And2 = 0xc0, // a & b
|
||||
Or2 = 0xfc, // a | b
|
||||
Xor2 = 0x3c, // a ^ b
|
||||
And3 = 0x80, // a & b & c
|
||||
Or3 = 0xfe, // a | b | c
|
||||
XorAnd = 0x60, // a & (b ^ c)
|
||||
XorOr = 0xf6, // a | (b ^ c)
|
||||
OrAnd = 0xe0, // a & (b | c)
|
||||
AndOr = 0xf8, // a | (b & c)
|
||||
Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true.
|
||||
Majority = 0xe8, // Popcount(a, b, c) >= 2
|
||||
Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off
|
||||
InverseGamble = 0x7e, // Inverse of Gamble
|
||||
Dot = 0x1a, // a ^ (c | (a & b))
|
||||
Mux = 0xca, // a ? b : c
|
||||
AndXor = 0x78, // a ^ (b & c)
|
||||
OrXor = 0x1e, // a ^ (b | c)
|
||||
Xor3 = 0x96, // a ^ b ^ c
|
||||
Dot = 0x1a, // a ^ (c | (a & b))
|
||||
Mux = 0xca, // a ? b : c
|
||||
AndXor = 0x78, // a ^ (b & c)
|
||||
OrXor = 0x1e, // a ^ (b | c)
|
||||
Xor3 = 0x96, // a ^ b ^ c
|
||||
}
|
||||
|
||||
public static Operand GetFromTruthTable(EmitterContext context, Operand srcA, Operand srcB, Operand srcC, int imm)
|
||||
|
@ -41,7 +40,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
Operand x = srcA;
|
||||
Operand y = srcB;
|
||||
Operand z = srcC;
|
||||
|
||||
|
||||
if ((i & 0x01) != 0)
|
||||
{
|
||||
(x, y) = (y, x);
|
||||
|
@ -98,6 +97,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
return imm switch
|
||||
{
|
||||
#pragma warning disable IDE0055 // Disable formatting
|
||||
TruthTable.False => Const(0),
|
||||
TruthTable.True => Const(-1),
|
||||
TruthTable.In => x,
|
||||
|
@ -118,7 +118,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
TruthTable.AndXor => context.BitwiseExclusiveOr(x, context.BitwiseAnd(y, z)),
|
||||
TruthTable.OrXor => context.BitwiseExclusiveOr(x, context.BitwiseOr(y, z)),
|
||||
TruthTable.Xor3 => context.BitwiseExclusiveOr(x, context.BitwiseExclusiveOr(y, z)),
|
||||
_ => null
|
||||
_ => null,
|
||||
#pragma warning restore IDE0055
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -138,4 +139,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
return (TruthTable)result;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue