Rewrite shader decoding stage (#2698)
* Rewrite shader decoding stage * Fix P2R constant buffer encoding * Fix PSET/PSETP * PR feedback * Log unimplemented shader instructions * Implement NOP * Remove using * PR feedback
This commit is contained in:
gdkchan
GitHub
parent
0510fde25a
commit
a7109c767b
168 changed files with 12022 additions and 6388 deletions
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@ -1,8 +1,8 @@
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using Ryujinx.Graphics.Shader.Instructions;
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using Ryujinx.Graphics.Shader.Translation;
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Runtime.CompilerServices;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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@ -95,32 +95,33 @@ namespace Ryujinx.Graphics.Shader.Decoders
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{
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// We should have blocks for all possible branch targets,
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// including those from SSY/PBK instructions.
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foreach (OpCodePush pushOp in currBlock.PushOpCodes)
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foreach (PushOpInfo pushOp in currBlock.PushOpCodes)
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{
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GetBlock(pushOp.GetAbsoluteAddress());
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GetBlock(pushOp.Op.GetAbsoluteAddress());
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}
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// Set child blocks. "Branch" is the block the branch instruction
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// points to (when taken), "Next" is the block at the next address,
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// executed when the branch is not taken. For Unconditional Branches
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// or end of program, Next is null.
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OpCode lastOp = currBlock.GetLastOp();
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InstOp lastOp = currBlock.GetLastOp();
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if (lastOp is OpCodeBranch opBr)
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if (lastOp.Name == InstName.Cal)
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{
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if (lastOp.Emitter == InstEmit.Cal)
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{
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EnqueueFunction(opBr.GetAbsoluteAddress());
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}
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else
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{
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currBlock.Branch = GetBlock(opBr.GetAbsoluteAddress());
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}
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EnqueueFunction(lastOp.GetAbsoluteAddress());
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}
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else if (lastOp.Name == InstName.Bra)
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{
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Block succBlock = GetBlock(lastOp.GetAbsoluteAddress());
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currBlock.Successors.Add(succBlock);
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succBlock.Predecessors.Add(currBlock);
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}
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if (!IsUnconditionalBranch(lastOp))
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if (!IsUnconditionalBranch(ref lastOp))
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{
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currBlock.Next = GetBlock(currBlock.EndAddress);
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Block succBlock = GetBlock(currBlock.EndAddress);
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currBlock.Successors.Insert(0, succBlock);
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succBlock.Predecessors.Add(currBlock);
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}
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}
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@ -146,33 +147,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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}
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// Try to find target for BRX (indirect branch) instructions.
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hasNewTarget = false;
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foreach (Block block in blocks)
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{
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if (block.GetLastOp() is OpCodeBranchIndir opBrIndir && opBrIndir.PossibleTargets.Count == 0)
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{
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ulong baseOffset = opBrIndir.Address + 8 + (ulong)opBrIndir.Offset;
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// An indirect branch could go anywhere,
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// try to get the possible target offsets from the constant buffer.
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(int cbBaseOffset, int cbOffsetsCount) = FindBrxTargetRange(block, opBrIndir.Ra.Index);
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if (cbOffsetsCount != 0)
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{
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hasNewTarget = true;
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}
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for (int i = 0; i < cbOffsetsCount; i++)
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{
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uint targetOffset = config.GpuAccessor.ConstantBuffer1Read(cbBaseOffset + i * 4);
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Block target = GetBlock(baseOffset + targetOffset);
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opBrIndir.PossibleTargets.Add(target);
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target.Predecessors.Add(block);
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}
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}
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}
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// Try to find targets for BRX (indirect branch) instructions.
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hasNewTarget = FindBrxTargets(config, blocks, GetBlock);
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// If we discovered new branch targets from the BRX instruction,
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// we need another round of decoding to decode the new blocks.
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@ -227,6 +203,10 @@ namespace Ryujinx.Graphics.Shader.Decoders
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IGpuAccessor gpuAccessor = config.GpuAccessor;
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ulong address = block.Address;
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int bufferOffset = 0;
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ReadOnlySpan<ulong> buffer = ReadOnlySpan<ulong>.Empty;
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InstOp op = default;
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do
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{
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@ -239,66 +219,75 @@ namespace Ryujinx.Graphics.Shader.Decoders
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if ((address & 0x1f) == 0)
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{
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address += 8;
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bufferOffset++;
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continue;
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}
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ulong opAddress = address;
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address += 8;
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long opCode = gpuAccessor.MemoryRead<long>(startAddress + opAddress);
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(InstEmitter emitter, OpCodeTable.MakeOp makeOp) = OpCodeTable.GetEmitter(opCode);
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if (emitter == null)
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if (bufferOffset >= buffer.Length)
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{
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// TODO: Warning, illegal encoding.
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block.OpCodes.Add(new OpCode(null, opAddress, opCode));
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continue;
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buffer = gpuAccessor.GetCode(startAddress + address, 8);
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bufferOffset = 0;
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}
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if (makeOp == null)
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{
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throw new ArgumentNullException(nameof(makeOp));
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}
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ulong opCode = buffer[bufferOffset++];
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OpCode op = makeOp(emitter, opAddress, opCode);
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op = InstTable.GetOp(address, opCode);
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// We check these patterns to figure out the presence of bindless access
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if ((op is OpCodeImage image && image.IsBindless) ||
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(op is OpCodeTxd txd && txd.IsBindless) ||
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(op is OpCodeTld4B) ||
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(emitter == InstEmit.TexB) ||
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(emitter == InstEmit.TldB) ||
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(emitter == InstEmit.TmmlB) ||
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(emitter == InstEmit.TxqB))
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if (op.Props.HasFlag(InstProps.TexB))
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{
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config.SetUsedFeature(FeatureFlags.Bindless);
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}
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// Populate used attributes.
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if (op is IOpCodeAttribute opAttr)
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if (op.Name == InstName.Ald || op.Name == InstName.Ast || op.Name == InstName.Ipa)
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{
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SetUserAttributeUses(config, opAttr);
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SetUserAttributeUses(config, op.Name, opCode);
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}
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else if (op.Name == InstName.Ssy || op.Name == InstName.Pbk)
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{
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block.AddPushOp(op);
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}
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block.OpCodes.Add(op);
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address += 8;
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}
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while (!IsControlFlowChange(block.GetLastOp()));
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while (!op.Props.HasFlag(InstProps.Bra));
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block.EndAddress = address;
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block.UpdatePushOps();
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}
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private static void SetUserAttributeUses(ShaderConfig config, IOpCodeAttribute opAttr)
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private static void SetUserAttributeUses(ShaderConfig config, InstName name, ulong opCode)
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{
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if (opAttr.Indexed)
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int offset;
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int count = 1;
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bool isStore = false;
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bool indexed = false;
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if (name == InstName.Ast)
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{
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if (opAttr.Emitter == InstEmit.Ast)
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InstAst opAst = new InstAst(opCode);
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count = (int)opAst.AlSize + 1;
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offset = opAst.Imm11;
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indexed = opAst.Phys;
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isStore = true;
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}
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else if (name == InstName.Ald)
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{
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InstAld opAld = new InstAld(opCode);
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count = (int)opAld.AlSize + 1;
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indexed = opAld.Phys;
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offset = opAld.Imm11;
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}
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else /* if (name == InstName.Ipa) */
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{
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InstIpa opIpa = new InstIpa(opCode);
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offset = opIpa.Imm10;
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indexed = opIpa.Idx;
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}
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if (indexed)
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{
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if (isStore)
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{
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config.SetAllOutputUserAttributes();
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}
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@ -309,14 +298,14 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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else
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{
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for (int elemIndex = 0; elemIndex < opAttr.Count; elemIndex++)
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for (int elemIndex = 0; elemIndex < count; elemIndex++)
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{
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int attr = opAttr.AttributeOffset + elemIndex * 4;
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int attr = offset + elemIndex * 4;
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if (attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd)
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{
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int index = (attr - AttributeConsts.UserAttributeBase) / 16;
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if (opAttr.Emitter == InstEmit.Ast)
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if (isStore)
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{
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config.SetOutputUserAttribute(index);
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}
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@ -329,27 +318,57 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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}
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private static bool IsUnconditionalBranch(OpCode opCode)
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public static bool IsUnconditionalBranch(ref InstOp op)
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{
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return IsUnconditional(opCode) && IsControlFlowChange(opCode);
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return IsUnconditional(ref op) && op.Props.HasFlag(InstProps.Bra);
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}
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private static bool IsUnconditional(OpCode opCode)
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private static bool IsUnconditional(ref InstOp op)
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{
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if (opCode is OpCodeExit op && op.Condition != Condition.Always)
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InstConditional condOp = new InstConditional(op.RawOpCode);
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if (op.Name == InstName.Exit && condOp.Ccc != Ccc.T)
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{
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return false;
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}
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return opCode.Predicate.Index == RegisterConsts.PredicateTrueIndex && !opCode.InvertPredicate;
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return condOp.Pred == RegisterConsts.PredicateTrueIndex && !condOp.PredInv;
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}
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private static bool IsControlFlowChange(OpCode opCode)
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private static bool FindBrxTargets(ShaderConfig config, IEnumerable<Block> blocks, Func<ulong, Block> getBlock)
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{
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return (opCode is OpCodeBranch opBranch && !opBranch.PushTarget) ||
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opCode is OpCodeBranchIndir ||
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opCode is OpCodeBranchPop ||
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opCode is OpCodeExit;
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bool hasNewTarget = false;
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foreach (Block block in blocks)
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{
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InstOp lastOp = block.GetLastOp();
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bool hasNext = block.HasNext();
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if (lastOp.Name == InstName.Brx && block.Successors.Count == (hasNext ? 1 : 0))
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{
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InstBrx opBrx = new InstBrx(lastOp.RawOpCode);
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ulong baseOffset = lastOp.GetAbsoluteAddress();
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// An indirect branch could go anywhere,
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// try to get the possible target offsets from the constant buffer.
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(int cbBaseOffset, int cbOffsetsCount) = FindBrxTargetRange(block, opBrx.SrcA);
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if (cbOffsetsCount != 0)
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{
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hasNewTarget = true;
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}
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for (int i = 0; i < cbOffsetsCount; i++)
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{
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uint targetOffset = config.GpuAccessor.ConstantBuffer1Read(cbBaseOffset + i * 4);
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Block target = getBlock(baseOffset + targetOffset);
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target.Predecessors.Add(block);
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block.Successors.Add(target);
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}
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}
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}
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return hasNewTarget;
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}
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private static (int, int) FindBrxTargetRange(Block block, int brxReg)
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@ -369,41 +388,51 @@ namespace Ryujinx.Graphics.Shader.Decoders
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HashSet<Block> visited = new HashSet<Block>();
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var ldcLocation = FindFirstRegWrite(visited, new BlockLocation(block, block.OpCodes.Count - 1), brxReg);
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if (ldcLocation.Block == null || ldcLocation.Block.OpCodes[ldcLocation.Index] is not OpCodeLdc opLdc)
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if (ldcLocation.Block == null || ldcLocation.Block.OpCodes[ldcLocation.Index].Name != InstName.Ldc)
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{
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return (0, 0);
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}
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if (opLdc.Slot != 1 || opLdc.IndexMode != CbIndexMode.Default)
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GetOp<InstLdc>(ldcLocation, out var opLdc);
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if (opLdc.CbufSlot != 1 || opLdc.AddressMode != 0)
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{
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return (0, 0);
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}
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var shlLocation = FindFirstRegWrite(visited, ldcLocation, opLdc.Ra.Index);
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if (shlLocation.Block == null || shlLocation.Block.OpCodes[shlLocation.Index] is not OpCodeAluImm opShl)
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var shlLocation = FindFirstRegWrite(visited, ldcLocation, opLdc.SrcA);
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if (shlLocation.Block == null || !shlLocation.IsImmInst(InstName.Shl))
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{
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return (0, 0);
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}
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if (opShl.Emitter != InstEmit.Shl || opShl.Immediate != 2)
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GetOp<InstShlI>(shlLocation, out var opShl);
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if (opShl.Imm20 != 2)
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{
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return (0, 0);
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}
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var imnmxLocation = FindFirstRegWrite(visited, shlLocation, opShl.Ra.Index);
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if (imnmxLocation.Block == null || imnmxLocation.Block.OpCodes[imnmxLocation.Index] is not OpCodeAluImm opImnmx)
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var imnmxLocation = FindFirstRegWrite(visited, shlLocation, opShl.SrcA);
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if (imnmxLocation.Block == null || !imnmxLocation.IsImmInst(InstName.Imnmx))
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{
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return (0, 0);
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}
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bool isImnmxS32 = opImnmx.RawOpCode.Extract(48);
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GetOp<InstImnmxI>(imnmxLocation, out var opImnmx);
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if (opImnmx.Emitter != InstEmit.Imnmx || isImnmxS32 || !opImnmx.Predicate39.IsPT || opImnmx.InvertP)
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if (opImnmx.Signed || opImnmx.SrcPred != RegisterConsts.PredicateTrueIndex || opImnmx.SrcPredInv)
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{
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return (0, 0);
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}
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return (opLdc.Offset, opImnmx.Immediate + 1);
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return (opLdc.CbufOffset, opImnmx.Imm20 + 1);
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}
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private static void GetOp<T>(BlockLocation location, out T op) where T : unmanaged
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{
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ulong rawOp = location.Block.OpCodes[location.Index].RawOpCode;
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op = Unsafe.As<ulong, T>(ref rawOp);
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}
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private struct BlockLocation
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@ -416,6 +445,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Block = block;
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Index = index;
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}
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public bool IsImmInst(InstName name)
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{
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InstOp op = Block.OpCodes[Index];
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return op.Name == name && op.Props.HasFlag(InstProps.Ib);
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}
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}
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private static BlockLocation FindFirstRegWrite(HashSet<Block> visited, BlockLocation location, int regIndex)
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@ -447,18 +482,20 @@ namespace Ryujinx.Graphics.Shader.Decoders
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return new BlockLocation(null, 0);
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}
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private static bool WritesToRegister(OpCode opCode, int regIndex)
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private static bool WritesToRegister(InstOp op, int regIndex)
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{
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// Predicate instruction only ever writes to predicate, so we shouldn't check those.
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if (opCode.Emitter == InstEmit.Fsetp ||
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opCode.Emitter == InstEmit.Hsetp2 ||
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opCode.Emitter == InstEmit.Isetp ||
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opCode.Emitter == InstEmit.R2p)
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if ((op.Props & (InstProps.Rd | InstProps.Rd2)) == 0)
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{
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return false;
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}
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return opCode is IOpCodeRd opRd && opRd.Rd.Index == regIndex;
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if (op.Props.HasFlag(InstProps.Rd2) && (byte)(op.RawOpCode >> 28) == regIndex)
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{
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return true;
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}
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return (byte)op.RawOpCode == regIndex;
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}
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private enum MergeType
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@ -527,14 +564,13 @@ namespace Ryujinx.Graphics.Shader.Decoders
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private static void PropagatePushOp(Dictionary<ulong, Block> blocks, Block currBlock, int pushOpIndex)
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{
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OpCodePush pushOp = currBlock.PushOpCodes[pushOpIndex];
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PushOpInfo pushOpInfo = currBlock.PushOpCodes[pushOpIndex];
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InstOp pushOp = pushOpInfo.Op;
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Block target = blocks[pushOp.GetAbsoluteAddress()];
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Stack<PathBlockState> workQueue = new Stack<PathBlockState>();
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HashSet<Block> visited = new HashSet<Block>();
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Stack<(ulong, MergeType)> branchStack = new Stack<(ulong, MergeType)>();
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void Push(PathBlockState pbs)
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@ -574,42 +610,30 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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int pushOpsCount = current.PushOpCodes.Count;
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if (pushOpsCount != 0)
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{
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Push(new PathBlockState(branchStack.Count));
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for (int index = pushOpIndex; index < pushOpsCount; index++)
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{
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OpCodePush currentPushOp = current.PushOpCodes[index];
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MergeType pushMergeType = currentPushOp.Emitter == InstEmit.Ssy ? MergeType.Sync : MergeType.Brk;
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InstOp currentPushOp = current.PushOpCodes[index].Op;
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MergeType pushMergeType = currentPushOp.Name == InstName.Ssy ? MergeType.Sync : MergeType.Brk;
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branchStack.Push((currentPushOp.GetAbsoluteAddress(), pushMergeType));
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}
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}
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pushOpIndex = 0;
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if (current.Next != null)
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bool hasNext = current.HasNext();
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if (hasNext)
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{
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Push(new PathBlockState(current.Next));
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Push(new PathBlockState(current.Successors[0]));
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}
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if (current.Branch != null)
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InstOp lastOp = current.GetLastOp();
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if (lastOp.Name == InstName.Sync || lastOp.Name == InstName.Brk)
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{
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Push(new PathBlockState(current.Branch));
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}
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else if (current.GetLastOp() is OpCodeBranchIndir brIndir)
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{
|
||||
// By adding them in descending order (sorted by address), we process the blocks
|
||||
// in order (of ascending address), since we work with a LIFO.
|
||||
foreach (Block possibleTarget in brIndir.PossibleTargets.OrderByDescending(x => x.Address))
|
||||
{
|
||||
Push(new PathBlockState(possibleTarget));
|
||||
}
|
||||
}
|
||||
else if (current.GetLastOp() is OpCodeBranchPop op)
|
||||
{
|
||||
MergeType popMergeType = op.Emitter == InstEmit.Sync ? MergeType.Sync : MergeType.Brk;
|
||||
MergeType popMergeType = lastOp.Name == InstName.Sync ? MergeType.Sync : MergeType.Brk;
|
||||
|
||||
bool found = true;
|
||||
ulong targetAddress = 0UL;
|
||||
|
|
@ -641,20 +665,32 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
{
|
||||
// If the entire stack was consumed, then the current pop instruction
|
||||
// just consumed the address from our push instruction.
|
||||
if (op.Targets.TryAdd(pushOp, op.Targets.Count))
|
||||
if (current.SyncTargets.TryAdd(pushOp.Address, new SyncTarget(pushOpInfo, current.SyncTargets.Count)))
|
||||
{
|
||||
pushOp.PopOps.Add(op, Local());
|
||||
pushOpInfo.Consumers.Add(current, Local());
|
||||
target.Predecessors.Add(current);
|
||||
current.Successors.Add(target);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Push the block itself into the work "queue" (well, it's a stack)
|
||||
// for processing.
|
||||
// Push the block itself into the work queue for processing.
|
||||
Push(new PathBlockState(blocks[targetAddress]));
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// By adding them in descending order (sorted by address), we process the blocks
|
||||
// in order (of ascending address), since we work with a LIFO.
|
||||
foreach (Block possibleTarget in current.Successors.OrderByDescending(x => x.Address))
|
||||
{
|
||||
if (!hasNext || possibleTarget != current.Successors[0])
|
||||
{
|
||||
Push(new PathBlockState(possibleTarget));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue