Rewrite shader decoding stage (#2698)
* Rewrite shader decoding stage * Fix P2R constant buffer encoding * Fix PSET/PSETP * PR feedback * Log unimplemented shader instructions * Implement NOP * Remove using * PR feedback
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168 changed files with 12022 additions and 6388 deletions
167
Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs
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167
Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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private const int PT = RegisterConsts.PredicateTrueIndex;
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public static void LopR(EmitterContext context)
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{
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InstLopR op = context.GetOp<InstLopR>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcReg(context, op.SrcB);
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EmitLop(context, op.Lop, op.PredicateOp, srcA, srcB, op.Dest, op.DestPred, op.NegA, op.NegB, op.X, op.WriteCC);
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}
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public static void LopI(EmitterContext context)
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{
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InstLopI op = context.GetOp<InstLopI>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, Imm20ToSInt(op.Imm20));
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EmitLop(context, op.LogicOp, op.PredicateOp, srcA, srcB, op.Dest, op.DestPred, op.NegA, op.NegB, op.X, op.WriteCC);
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}
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public static void LopC(EmitterContext context)
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{
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InstLopC op = context.GetOp<InstLopC>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
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EmitLop(context, op.LogicOp, op.PredicateOp, srcA, srcB, op.Dest, op.DestPred, op.NegA, op.NegB, op.X, op.WriteCC);
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}
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public static void Lop32i(EmitterContext context)
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{
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InstLop32i op = context.GetOp<InstLop32i>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, op.Imm32);
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EmitLop(context, op.LogicOp, PredicateOp.F, srcA, srcB, op.Dest, PT, op.NegA, op.NegB, op.X, op.WriteCC);
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}
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public static void Lop3R(EmitterContext context)
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{
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InstLop3R op = context.GetOp<InstLop3R>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcReg(context, op.SrcB);
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var srcC = GetSrcReg(context, op.SrcC);
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EmitLop3(context, op.Imm, op.PredicateOp, srcA, srcB, srcC, op.Dest, op.DestPred, op.X, op.WriteCC);
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}
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public static void Lop3I(EmitterContext context)
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{
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InstLop3I op = context.GetOp<InstLop3I>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, Imm20ToSInt(op.Imm20));
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var srcC = GetSrcReg(context, op.SrcC);
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EmitLop3(context, op.Imm, PredicateOp.F, srcA, srcB, srcC, op.Dest, PT, false, op.WriteCC);
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}
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public static void Lop3C(EmitterContext context)
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{
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InstLop3C op = context.GetOp<InstLop3C>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
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var srcC = GetSrcReg(context, op.SrcC);
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EmitLop3(context, op.Imm, PredicateOp.F, srcA, srcB, srcC, op.Dest, PT, false, op.WriteCC);
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}
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private static void EmitLop(
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EmitterContext context,
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LogicOp logicOp,
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PredicateOp predOp,
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Operand srcA,
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Operand srcB,
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int rd,
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int destPred,
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bool invertA,
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bool invertB,
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bool extended,
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bool writeCC)
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{
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srcA = context.BitwiseNot(srcA, invertA);
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srcB = context.BitwiseNot(srcB, invertB);
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Operand res = logicOp switch
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{
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LogicOp.And => res = context.BitwiseAnd(srcA, srcB),
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LogicOp.Or => res = context.BitwiseOr(srcA, srcB),
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LogicOp.Xor => res = context.BitwiseExclusiveOr(srcA, srcB),
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_ => srcB
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};
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EmitLopPredWrite(context, res, predOp, destPred);
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context.Copy(GetDest(rd), res);
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SetZnFlags(context, res, writeCC, extended);
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}
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private static void EmitLop3(
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EmitterContext context,
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int truthTable,
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PredicateOp predOp,
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Operand srcA,
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Operand srcB,
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Operand srcC,
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int rd,
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int destPred,
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bool extended,
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bool writeCC)
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{
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Operand res = Lop3Expression.GetFromTruthTable(context, srcA, srcB, srcC, truthTable);
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EmitLopPredWrite(context, res, predOp, destPred);
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context.Copy(GetDest(rd), res);
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SetZnFlags(context, res, writeCC, extended);
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}
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private static void EmitLopPredWrite(EmitterContext context, Operand result, PredicateOp predOp, int pred)
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{
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if (pred != RegisterConsts.PredicateTrueIndex)
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{
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Operand pRes;
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if (predOp == PredicateOp.F)
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{
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pRes = Const(IrConsts.False);
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}
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else if (predOp == PredicateOp.T)
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{
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pRes = Const(IrConsts.True);
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}
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else if (predOp == PredicateOp.Z)
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{
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pRes = context.ICompareEqual(result, Const(0));
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}
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else /* if (predOp == Pop.Nz) */
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{
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pRes = context.ICompareNotEqual(result, Const(0));
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}
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context.Copy(Register(pred, RegisterType.Predicate), pRes);
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}
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}
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}
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}
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