Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan
emmauss
parent
1ba58e9942
commit
a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
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@ -1,7 +1,6 @@
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using ChocolArm64;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using NUnit.Framework;
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@ -9,24 +8,24 @@ using Ryujinx.Tests.Unicorn;
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using System;
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using System.Runtime.InteropServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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using System.Threading;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public class CpuTest
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{
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protected long Position { get; private set; }
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private long _size;
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private ulong _currAddress;
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private long _size;
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private long _entryPoint;
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private ulong _entryPoint;
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private IntPtr _ramPointer;
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private MemoryManager _memory;
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private CpuThread _thread;
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private ExecutionContext _context;
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private Translator _translator;
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private static bool _unicornAvailable;
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private UnicornAArch64 _unicornEmu;
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@ -44,24 +43,24 @@ namespace Ryujinx.Tests.Cpu
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[SetUp]
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public void Setup()
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{
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Position = 0x1000;
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_size = 0x1000;
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_currAddress = 0x1000;
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_size = 0x1000;
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_entryPoint = Position;
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_entryPoint = _currAddress;
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_ramPointer = Marshal.AllocHGlobal(new IntPtr(_size));
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_memory = new MemoryManager(_ramPointer);
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_memory.Map(Position, 0, _size);
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_memory.Map((long)_currAddress, 0, _size);
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Translator translator = new Translator(_memory);
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_context = new ExecutionContext();
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_thread = new CpuThread(translator, _memory, _entryPoint);
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_translator = new Translator(_memory);
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if (_unicornAvailable)
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{
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_unicornEmu = new UnicornAArch64();
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_unicornEmu.MemoryMap((ulong)Position, (ulong)_size, MemoryPermission.READ | MemoryPermission.EXEC);
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_unicornEmu.PC = (ulong)_entryPoint;
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_unicornEmu.MemoryMap(_currAddress, (ulong)_size, MemoryPermission.READ | MemoryPermission.EXEC);
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_unicornEmu.PC = _entryPoint;
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}
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}
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@ -70,7 +69,8 @@ namespace Ryujinx.Tests.Cpu
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{
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Marshal.FreeHGlobal(_ramPointer);
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_memory = null;
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_thread = null;
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_context = null;
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_translator = null;
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_unicornEmu = null;
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}
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@ -82,51 +82,61 @@ namespace Ryujinx.Tests.Cpu
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protected void Opcode(uint opcode)
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{
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_thread.Memory.WriteUInt32(Position, opcode);
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_memory.WriteUInt32((long)_currAddress, opcode);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite32((ulong)Position, opcode);
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_unicornEmu.MemoryWrite32((ulong)_currAddress, opcode);
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}
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Position += 4;
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_currAddress += 4;
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}
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protected void SetThreadState(ulong x0 = 0, ulong x1 = 0, ulong x2 = 0, ulong x3 = 0, ulong x31 = 0,
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v4 = default(Vector128<float>),
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Vector128<float> v5 = default(Vector128<float>),
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Vector128<float> v30 = default(Vector128<float>),
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Vector128<float> v31 = default(Vector128<float>),
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bool overflow = false, bool carry = false, bool zero = false, bool negative = false,
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int fpcr = 0x0, int fpsr = 0x0)
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protected ExecutionContext GetContext() => _context;
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protected void SetContext(ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default(V128),
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V128 v1 = default(V128),
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V128 v2 = default(V128),
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V128 v3 = default(V128),
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V128 v4 = default(V128),
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V128 v5 = default(V128),
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V128 v30 = default(V128),
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V128 v31 = default(V128),
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0)
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{
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_thread.ThreadState.X0 = x0;
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_thread.ThreadState.X1 = x1;
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_thread.ThreadState.X2 = x2;
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_thread.ThreadState.X3 = x3;
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_context.SetX(0, x0);
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_context.SetX(1, x1);
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_context.SetX(2, x2);
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_context.SetX(3, x3);
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_thread.ThreadState.X31 = x31;
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_context.SetX(31, x31);
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_thread.ThreadState.V0 = v0;
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_thread.ThreadState.V1 = v1;
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_thread.ThreadState.V2 = v2;
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_thread.ThreadState.V3 = v3;
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_thread.ThreadState.V4 = v4;
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_thread.ThreadState.V5 = v5;
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_thread.ThreadState.V30 = v30;
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_thread.ThreadState.V31 = v31;
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_context.SetV(0, v0);
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_context.SetV(1, v1);
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_context.SetV(2, v2);
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_context.SetV(3, v3);
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_context.SetV(4, v4);
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_context.SetV(5, v5);
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_context.SetV(30, v30);
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_context.SetV(31, v31);
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_thread.ThreadState.Overflow = overflow;
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_thread.ThreadState.Carry = carry;
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_thread.ThreadState.Zero = zero;
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_thread.ThreadState.Negative = negative;
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_context.SetPstateFlag(PState.VFlag, overflow);
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_context.SetPstateFlag(PState.CFlag, carry);
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_context.SetPstateFlag(PState.ZFlag, zero);
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_context.SetPstateFlag(PState.NFlag, negative);
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_thread.ThreadState.Fpcr = fpcr;
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_thread.ThreadState.Fpsr = fpsr;
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_context.Fpcr = (FPCR)fpcr;
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_context.Fpsr = (FPSR)fpsr;
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if (_unicornAvailable)
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{
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@ -137,14 +147,14 @@ namespace Ryujinx.Tests.Cpu
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_unicornEmu.SP = x31;
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_unicornEmu.Q[0] = v0;
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_unicornEmu.Q[1] = v1;
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_unicornEmu.Q[2] = v2;
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_unicornEmu.Q[3] = v3;
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_unicornEmu.Q[4] = v4;
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_unicornEmu.Q[5] = v5;
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_unicornEmu.Q[30] = v30;
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_unicornEmu.Q[31] = v31;
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[30] = V128ToSimdValue(v30);
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_unicornEmu.Q[31] = V128ToSimdValue(v31);
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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@ -158,43 +168,41 @@ namespace Ryujinx.Tests.Cpu
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protected void ExecuteOpcodes()
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{
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using (ManualResetEvent wait = new ManualResetEvent(false))
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{
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_thread.ThreadState.Break += (sender, e) => _thread.StopExecution();
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_thread.WorkFinished += (sender, e) => wait.Set();
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_thread.Execute();
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wait.WaitOne();
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}
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_translator.Execute(_context, _entryPoint);
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if (_unicornAvailable)
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{
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_unicornEmu.RunForCount((ulong)(Position - _entryPoint - 8) / 4);
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_unicornEmu.RunForCount((ulong)(_currAddress - _entryPoint - 4) / 4);
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}
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}
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protected CpuThreadState GetThreadState() => _thread.ThreadState;
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protected CpuThreadState SingleOpcode(uint opcode,
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ulong x0 = 0, ulong x1 = 0, ulong x2 = 0, ulong x3 = 0, ulong x31 = 0,
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Vector128<float> v0 = default(Vector128<float>),
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Vector128<float> v1 = default(Vector128<float>),
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Vector128<float> v2 = default(Vector128<float>),
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Vector128<float> v3 = default(Vector128<float>),
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Vector128<float> v4 = default(Vector128<float>),
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Vector128<float> v5 = default(Vector128<float>),
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Vector128<float> v30 = default(Vector128<float>),
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Vector128<float> v31 = default(Vector128<float>),
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bool overflow = false, bool carry = false, bool zero = false, bool negative = false,
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int fpcr = 0x0, int fpsr = 0x0)
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protected ExecutionContext SingleOpcode(uint opcode,
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ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default(V128),
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V128 v1 = default(V128),
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V128 v2 = default(V128),
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V128 v3 = default(V128),
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V128 v4 = default(V128),
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V128 v5 = default(V128),
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V128 v30 = default(V128),
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V128 v31 = default(V128),
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0)
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{
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Opcode(opcode);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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SetThreadState(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr);
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SetContext(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr);
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ExecuteOpcodes();
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return GetThreadState();
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return GetContext();
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}
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/// <summary>Rounding Mode control field.</summary>
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@ -279,101 +287,101 @@ namespace Ryujinx.Tests.Cpu
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ManageFpSkips(fpSkips);
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}
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Assert.That(_thread.ThreadState.X0, Is.EqualTo(_unicornEmu.X[0]));
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Assert.That(_thread.ThreadState.X1, Is.EqualTo(_unicornEmu.X[1]));
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Assert.That(_thread.ThreadState.X2, Is.EqualTo(_unicornEmu.X[2]));
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Assert.That(_thread.ThreadState.X3, Is.EqualTo(_unicornEmu.X[3]));
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Assert.That(_thread.ThreadState.X4, Is.EqualTo(_unicornEmu.X[4]));
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Assert.That(_thread.ThreadState.X5, Is.EqualTo(_unicornEmu.X[5]));
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Assert.That(_thread.ThreadState.X6, Is.EqualTo(_unicornEmu.X[6]));
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Assert.That(_thread.ThreadState.X7, Is.EqualTo(_unicornEmu.X[7]));
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Assert.That(_thread.ThreadState.X8, Is.EqualTo(_unicornEmu.X[8]));
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Assert.That(_thread.ThreadState.X9, Is.EqualTo(_unicornEmu.X[9]));
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Assert.That(_thread.ThreadState.X10, Is.EqualTo(_unicornEmu.X[10]));
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Assert.That(_thread.ThreadState.X11, Is.EqualTo(_unicornEmu.X[11]));
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Assert.That(_thread.ThreadState.X12, Is.EqualTo(_unicornEmu.X[12]));
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Assert.That(_thread.ThreadState.X13, Is.EqualTo(_unicornEmu.X[13]));
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Assert.That(_thread.ThreadState.X14, Is.EqualTo(_unicornEmu.X[14]));
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Assert.That(_thread.ThreadState.X15, Is.EqualTo(_unicornEmu.X[15]));
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Assert.That(_thread.ThreadState.X16, Is.EqualTo(_unicornEmu.X[16]));
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Assert.That(_thread.ThreadState.X17, Is.EqualTo(_unicornEmu.X[17]));
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Assert.That(_thread.ThreadState.X18, Is.EqualTo(_unicornEmu.X[18]));
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Assert.That(_thread.ThreadState.X19, Is.EqualTo(_unicornEmu.X[19]));
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Assert.That(_thread.ThreadState.X20, Is.EqualTo(_unicornEmu.X[20]));
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Assert.That(_thread.ThreadState.X21, Is.EqualTo(_unicornEmu.X[21]));
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Assert.That(_thread.ThreadState.X22, Is.EqualTo(_unicornEmu.X[22]));
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Assert.That(_thread.ThreadState.X23, Is.EqualTo(_unicornEmu.X[23]));
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Assert.That(_thread.ThreadState.X24, Is.EqualTo(_unicornEmu.X[24]));
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Assert.That(_thread.ThreadState.X25, Is.EqualTo(_unicornEmu.X[25]));
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Assert.That(_thread.ThreadState.X26, Is.EqualTo(_unicornEmu.X[26]));
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Assert.That(_thread.ThreadState.X27, Is.EqualTo(_unicornEmu.X[27]));
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Assert.That(_thread.ThreadState.X28, Is.EqualTo(_unicornEmu.X[28]));
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Assert.That(_thread.ThreadState.X29, Is.EqualTo(_unicornEmu.X[29]));
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Assert.That(_thread.ThreadState.X30, Is.EqualTo(_unicornEmu.X[30]));
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Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.X[0]));
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Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.X[1]));
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Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.X[2]));
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Assert.That(_context.GetX(3), Is.EqualTo(_unicornEmu.X[3]));
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Assert.That(_context.GetX(4), Is.EqualTo(_unicornEmu.X[4]));
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Assert.That(_context.GetX(5), Is.EqualTo(_unicornEmu.X[5]));
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Assert.That(_context.GetX(6), Is.EqualTo(_unicornEmu.X[6]));
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Assert.That(_context.GetX(7), Is.EqualTo(_unicornEmu.X[7]));
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Assert.That(_context.GetX(8), Is.EqualTo(_unicornEmu.X[8]));
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Assert.That(_context.GetX(9), Is.EqualTo(_unicornEmu.X[9]));
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Assert.That(_context.GetX(10), Is.EqualTo(_unicornEmu.X[10]));
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Assert.That(_context.GetX(11), Is.EqualTo(_unicornEmu.X[11]));
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Assert.That(_context.GetX(12), Is.EqualTo(_unicornEmu.X[12]));
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Assert.That(_context.GetX(13), Is.EqualTo(_unicornEmu.X[13]));
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Assert.That(_context.GetX(14), Is.EqualTo(_unicornEmu.X[14]));
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Assert.That(_context.GetX(15), Is.EqualTo(_unicornEmu.X[15]));
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Assert.That(_context.GetX(16), Is.EqualTo(_unicornEmu.X[16]));
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Assert.That(_context.GetX(17), Is.EqualTo(_unicornEmu.X[17]));
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Assert.That(_context.GetX(18), Is.EqualTo(_unicornEmu.X[18]));
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Assert.That(_context.GetX(19), Is.EqualTo(_unicornEmu.X[19]));
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Assert.That(_context.GetX(20), Is.EqualTo(_unicornEmu.X[20]));
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Assert.That(_context.GetX(21), Is.EqualTo(_unicornEmu.X[21]));
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Assert.That(_context.GetX(22), Is.EqualTo(_unicornEmu.X[22]));
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Assert.That(_context.GetX(23), Is.EqualTo(_unicornEmu.X[23]));
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Assert.That(_context.GetX(24), Is.EqualTo(_unicornEmu.X[24]));
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Assert.That(_context.GetX(25), Is.EqualTo(_unicornEmu.X[25]));
|
||||
Assert.That(_context.GetX(26), Is.EqualTo(_unicornEmu.X[26]));
|
||||
Assert.That(_context.GetX(27), Is.EqualTo(_unicornEmu.X[27]));
|
||||
Assert.That(_context.GetX(28), Is.EqualTo(_unicornEmu.X[28]));
|
||||
Assert.That(_context.GetX(29), Is.EqualTo(_unicornEmu.X[29]));
|
||||
Assert.That(_context.GetX(30), Is.EqualTo(_unicornEmu.X[30]));
|
||||
|
||||
Assert.That(_thread.ThreadState.X31, Is.EqualTo(_unicornEmu.SP));
|
||||
Assert.That(_context.GetX(31), Is.EqualTo(_unicornEmu.SP));
|
||||
|
||||
if (fpTolerances == FpTolerances.None)
|
||||
{
|
||||
Assert.That(_thread.ThreadState.V0, Is.EqualTo(_unicornEmu.Q[0]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
|
||||
}
|
||||
else
|
||||
{
|
||||
ManageFpTolerances(fpTolerances);
|
||||
}
|
||||
Assert.That(_thread.ThreadState.V1, Is.EqualTo(_unicornEmu.Q[1]));
|
||||
Assert.That(_thread.ThreadState.V2, Is.EqualTo(_unicornEmu.Q[2]));
|
||||
Assert.That(_thread.ThreadState.V3, Is.EqualTo(_unicornEmu.Q[3]));
|
||||
Assert.That(_thread.ThreadState.V4, Is.EqualTo(_unicornEmu.Q[4]));
|
||||
Assert.That(_thread.ThreadState.V5, Is.EqualTo(_unicornEmu.Q[5]));
|
||||
Assert.That(_thread.ThreadState.V6, Is.EqualTo(_unicornEmu.Q[6]));
|
||||
Assert.That(_thread.ThreadState.V7, Is.EqualTo(_unicornEmu.Q[7]));
|
||||
Assert.That(_thread.ThreadState.V8, Is.EqualTo(_unicornEmu.Q[8]));
|
||||
Assert.That(_thread.ThreadState.V9, Is.EqualTo(_unicornEmu.Q[9]));
|
||||
Assert.That(_thread.ThreadState.V10, Is.EqualTo(_unicornEmu.Q[10]));
|
||||
Assert.That(_thread.ThreadState.V11, Is.EqualTo(_unicornEmu.Q[11]));
|
||||
Assert.That(_thread.ThreadState.V12, Is.EqualTo(_unicornEmu.Q[12]));
|
||||
Assert.That(_thread.ThreadState.V13, Is.EqualTo(_unicornEmu.Q[13]));
|
||||
Assert.That(_thread.ThreadState.V14, Is.EqualTo(_unicornEmu.Q[14]));
|
||||
Assert.That(_thread.ThreadState.V15, Is.EqualTo(_unicornEmu.Q[15]));
|
||||
Assert.That(_thread.ThreadState.V16, Is.EqualTo(_unicornEmu.Q[16]));
|
||||
Assert.That(_thread.ThreadState.V17, Is.EqualTo(_unicornEmu.Q[17]));
|
||||
Assert.That(_thread.ThreadState.V18, Is.EqualTo(_unicornEmu.Q[18]));
|
||||
Assert.That(_thread.ThreadState.V19, Is.EqualTo(_unicornEmu.Q[19]));
|
||||
Assert.That(_thread.ThreadState.V20, Is.EqualTo(_unicornEmu.Q[20]));
|
||||
Assert.That(_thread.ThreadState.V21, Is.EqualTo(_unicornEmu.Q[21]));
|
||||
Assert.That(_thread.ThreadState.V22, Is.EqualTo(_unicornEmu.Q[22]));
|
||||
Assert.That(_thread.ThreadState.V23, Is.EqualTo(_unicornEmu.Q[23]));
|
||||
Assert.That(_thread.ThreadState.V24, Is.EqualTo(_unicornEmu.Q[24]));
|
||||
Assert.That(_thread.ThreadState.V25, Is.EqualTo(_unicornEmu.Q[25]));
|
||||
Assert.That(_thread.ThreadState.V26, Is.EqualTo(_unicornEmu.Q[26]));
|
||||
Assert.That(_thread.ThreadState.V27, Is.EqualTo(_unicornEmu.Q[27]));
|
||||
Assert.That(_thread.ThreadState.V28, Is.EqualTo(_unicornEmu.Q[28]));
|
||||
Assert.That(_thread.ThreadState.V29, Is.EqualTo(_unicornEmu.Q[29]));
|
||||
Assert.That(_thread.ThreadState.V30, Is.EqualTo(_unicornEmu.Q[30]));
|
||||
Assert.That(_thread.ThreadState.V31, Is.EqualTo(_unicornEmu.Q[31]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(4)), Is.EqualTo(_unicornEmu.Q[4]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(5)), Is.EqualTo(_unicornEmu.Q[5]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(6)), Is.EqualTo(_unicornEmu.Q[6]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(7)), Is.EqualTo(_unicornEmu.Q[7]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(8)), Is.EqualTo(_unicornEmu.Q[8]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(9)), Is.EqualTo(_unicornEmu.Q[9]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(10)), Is.EqualTo(_unicornEmu.Q[10]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(11)), Is.EqualTo(_unicornEmu.Q[11]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(12)), Is.EqualTo(_unicornEmu.Q[12]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(13)), Is.EqualTo(_unicornEmu.Q[13]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(14)), Is.EqualTo(_unicornEmu.Q[14]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(15)), Is.EqualTo(_unicornEmu.Q[15]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(16)), Is.EqualTo(_unicornEmu.Q[16]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(17)), Is.EqualTo(_unicornEmu.Q[17]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(18)), Is.EqualTo(_unicornEmu.Q[18]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(19)), Is.EqualTo(_unicornEmu.Q[19]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(20)), Is.EqualTo(_unicornEmu.Q[20]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(21)), Is.EqualTo(_unicornEmu.Q[21]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(22)), Is.EqualTo(_unicornEmu.Q[22]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(23)), Is.EqualTo(_unicornEmu.Q[23]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(24)), Is.EqualTo(_unicornEmu.Q[24]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(25)), Is.EqualTo(_unicornEmu.Q[25]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(26)), Is.EqualTo(_unicornEmu.Q[26]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(27)), Is.EqualTo(_unicornEmu.Q[27]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(28)), Is.EqualTo(_unicornEmu.Q[28]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(29)), Is.EqualTo(_unicornEmu.Q[29]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(30)), Is.EqualTo(_unicornEmu.Q[30]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(31)), Is.EqualTo(_unicornEmu.Q[31]));
|
||||
|
||||
Assert.That(_thread.ThreadState.Fpcr, Is.EqualTo(_unicornEmu.Fpcr));
|
||||
Assert.That(_thread.ThreadState.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask));
|
||||
Assert.That((int)_context.Fpcr, Is.EqualTo(_unicornEmu.Fpcr));
|
||||
Assert.That((int)_context.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask));
|
||||
|
||||
Assert.That(_thread.ThreadState.Overflow, Is.EqualTo(_unicornEmu.OverflowFlag));
|
||||
Assert.That(_thread.ThreadState.Carry, Is.EqualTo(_unicornEmu.CarryFlag));
|
||||
Assert.That(_thread.ThreadState.Zero, Is.EqualTo(_unicornEmu.ZeroFlag));
|
||||
Assert.That(_thread.ThreadState.Negative, Is.EqualTo(_unicornEmu.NegativeFlag));
|
||||
Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag));
|
||||
Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag));
|
||||
Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag));
|
||||
Assert.That(_context.GetPstateFlag(PState.NFlag), Is.EqualTo(_unicornEmu.NegativeFlag));
|
||||
}
|
||||
|
||||
private void ManageFpSkips(FpSkips fpSkips)
|
||||
{
|
||||
if (fpSkips.HasFlag(FpSkips.IfNaNS))
|
||||
{
|
||||
if (float.IsNaN(VectorExtractSingle(_unicornEmu.Q[0], (byte)0)))
|
||||
if (float.IsNaN(_unicornEmu.Q[0].AsFloat()))
|
||||
{
|
||||
Assert.Ignore("NaN test.");
|
||||
}
|
||||
}
|
||||
else if (fpSkips.HasFlag(FpSkips.IfNaND))
|
||||
{
|
||||
if (double.IsNaN(VectorExtractDouble(_unicornEmu.Q[0], (byte)0)))
|
||||
if (double.IsNaN(_unicornEmu.Q[0].AsDouble()))
|
||||
{
|
||||
Assert.Ignore("NaN test.");
|
||||
}
|
||||
|
|
@ -398,158 +406,68 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
private void ManageFpTolerances(FpTolerances fpTolerances)
|
||||
{
|
||||
if (!Is.EqualTo(_unicornEmu.Q[0]).ApplyTo(_thread.ThreadState.V0).IsSuccess)
|
||||
bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
|
||||
bool IsNormalOrSubnormalD(double d) => double.IsNormal(d) || double.IsSubnormal(d);
|
||||
|
||||
if (!Is.EqualTo(_unicornEmu.Q[0]).ApplyTo(V128ToSimdValue(_context.GetV(0))).IsSuccess)
|
||||
{
|
||||
if (fpTolerances == FpTolerances.UpToOneUlpsS)
|
||||
{
|
||||
if (IsNormalOrSubnormalS(VectorExtractSingle(_unicornEmu.Q[0], (byte)0)) &&
|
||||
IsNormalOrSubnormalS(VectorExtractSingle(_thread.ThreadState.V0, (byte)0)))
|
||||
if (IsNormalOrSubnormalS(_unicornEmu.Q[0].AsFloat()) &&
|
||||
IsNormalOrSubnormalS(_context.GetV(0).AsFloat()))
|
||||
{
|
||||
Assert.That (VectorExtractSingle(_thread.ThreadState.V0, (byte)0),
|
||||
Is.EqualTo(VectorExtractSingle(_unicornEmu.Q[0], (byte)0)).Within(1).Ulps);
|
||||
Assert.That (VectorExtractSingle(_thread.ThreadState.V0, (byte)1),
|
||||
Is.EqualTo(VectorExtractSingle(_unicornEmu.Q[0], (byte)1)).Within(1).Ulps);
|
||||
Assert.That (VectorExtractSingle(_thread.ThreadState.V0, (byte)2),
|
||||
Is.EqualTo(VectorExtractSingle(_unicornEmu.Q[0], (byte)2)).Within(1).Ulps);
|
||||
Assert.That (VectorExtractSingle(_thread.ThreadState.V0, (byte)3),
|
||||
Is.EqualTo(VectorExtractSingle(_unicornEmu.Q[0], (byte)3)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetFloat(0),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetFloat(1),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetFloat(2),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetFloat(3),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps);
|
||||
|
||||
Console.WriteLine(fpTolerances);
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That(_thread.ThreadState.V0, Is.EqualTo(_unicornEmu.Q[0]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
|
||||
}
|
||||
}
|
||||
|
||||
if (fpTolerances == FpTolerances.UpToOneUlpsD)
|
||||
{
|
||||
if (IsNormalOrSubnormalD(VectorExtractDouble(_unicornEmu.Q[0], (byte)0)) &&
|
||||
IsNormalOrSubnormalD(VectorExtractDouble(_thread.ThreadState.V0, (byte)0)))
|
||||
if (IsNormalOrSubnormalD(_unicornEmu.Q[0].AsDouble()) &&
|
||||
IsNormalOrSubnormalD(_context.GetV(0).AsDouble()))
|
||||
{
|
||||
Assert.That (VectorExtractDouble(_thread.ThreadState.V0, (byte)0),
|
||||
Is.EqualTo(VectorExtractDouble(_unicornEmu.Q[0], (byte)0)).Within(1).Ulps);
|
||||
Assert.That (VectorExtractDouble(_thread.ThreadState.V0, (byte)1),
|
||||
Is.EqualTo(VectorExtractDouble(_unicornEmu.Q[0], (byte)1)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetDouble(0),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps);
|
||||
Assert.That (_context.GetV(0).GetDouble(1),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps);
|
||||
|
||||
Console.WriteLine(fpTolerances);
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That(_thread.ThreadState.V0, Is.EqualTo(_unicornEmu.Q[0]));
|
||||
Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
|
||||
|
||||
bool IsNormalOrSubnormalD(double d) => double.IsNormal(d) || double.IsSubnormal(d);
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0(double e0)
|
||||
private static SimdValue V128ToSimdValue(V128 value)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(e0)));
|
||||
return new SimdValue(value.GetUInt64(0), value.GetUInt64(1));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0E1(double e0, double e1)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
protected static V128 MakeVectorScalar(float value) => new V128(value);
|
||||
protected static V128 MakeVectorScalar(double value) => new V128(value);
|
||||
|
||||
return Sse.StaticCast<long, float>(
|
||||
Sse2.SetVector128(BitConverter.DoubleToInt64Bits(e1), BitConverter.DoubleToInt64Bits(e0)));
|
||||
}
|
||||
protected static V128 MakeVectorE0(ulong e0) => new V128(e0, 0);
|
||||
protected static V128 MakeVectorE1(ulong e1) => new V128(0, e1);
|
||||
|
||||
protected static Vector128<float> MakeVectorE1(double e1)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new V128(e0, e1);
|
||||
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(e1), 0));
|
||||
}
|
||||
|
||||
protected static float VectorExtractSingle(Vector128<float> vector, byte index)
|
||||
{
|
||||
if (!Sse41.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
int value = Sse41.Extract(Sse.StaticCast<float, int>(vector), index);
|
||||
|
||||
return BitConverter.Int32BitsToSingle(value);
|
||||
}
|
||||
|
||||
protected static double VectorExtractDouble(Vector128<float> vector, byte index)
|
||||
{
|
||||
if (!Sse41.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
long value = Sse41.Extract(Sse.StaticCast<float, long>(vector), index);
|
||||
|
||||
return BitConverter.Int64BitsToDouble(value);
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0(ulong e0)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, e0));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0E1(ulong e0, ulong e1)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(e1, e0));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE1(ulong e1)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(e1, 0));
|
||||
}
|
||||
|
||||
protected static ulong GetVectorE0(Vector128<float> vector)
|
||||
{
|
||||
if (!Sse41.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse41.Extract(Sse.StaticCast<float, ulong>(vector), (byte)0);
|
||||
}
|
||||
|
||||
protected static ulong GetVectorE1(Vector128<float> vector)
|
||||
{
|
||||
if (!Sse41.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
return Sse41.Extract(Sse.StaticCast<float, ulong>(vector), (byte)1);
|
||||
}
|
||||
protected static ulong GetVectorE0(V128 vector) => vector.GetUInt64(0);
|
||||
protected static ulong GetVectorE1(V128 vector) => vector.GetUInt64(1);
|
||||
|
||||
protected static ushort GenNormalH()
|
||||
{
|
||||
|
|
|
|||
238
Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
Normal file
238
Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
#define AluBinary
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("AluBinary")]
|
||||
public sealed class CpuTestAluBinary : CpuTest
|
||||
{
|
||||
#if AluBinary
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("CRC32X <Wd>, <Wn>, <Xm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32x([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32W <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32w([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32H <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32h([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32B <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32b([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CX <Wd>, <Wn>, <Xm>")]
|
||||
public void Crc32cx([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CW <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32cw([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CH <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32ch([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CB <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32cb([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SDIV <Xd>, <Xn>, <Xm>")]
|
||||
public void Sdiv_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SDIV <Wd>, <Wn>, <Wm>")]
|
||||
public void Sdiv_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UDIV <Xd>, <Xn>, <Xm>")]
|
||||
public void Udiv_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UDIV <Wd>, <Wn>, <Wm>")]
|
||||
public void Udiv_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -394,154 +394,6 @@ namespace Ryujinx.Tests.Cpu
|
|||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32X <Wd>, <Wn>, <Xm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32x([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32W <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32w([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32H <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32h([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32B <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
||||
public void Crc32b([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CX <Wd>, <Wn>, <Xm>")]
|
||||
public void Crc32cx([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CW <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32cw([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CH <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32ch([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CRC32CB <Wd>, <Wn>, <Wm>")]
|
||||
public void Crc32cb([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>}")]
|
||||
public void Eon_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
|
|
@ -954,44 +806,6 @@ namespace Ryujinx.Tests.Cpu
|
|||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SDIV <Xd>, <Xn>, <Xm>")]
|
||||
public void Sdiv_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SDIV <Wd>, <Wn>, <Wm>")]
|
||||
public void Sdiv_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}")]
|
||||
public void Sub_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
|
|
@ -1079,44 +893,6 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UDIV <Xd>, <Xn>, <Xm>")]
|
||||
public void Udiv_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UDIV <Wd>, <Wn>, <Wm>")]
|
||||
public void Udiv_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
#define Misc
|
||||
|
||||
using ChocolArm64.State;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("Misc")]
|
||||
|
|
@ -32,10 +30,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
opCset |= ((cond & 15) << 12);
|
||||
|
||||
SetThreadState(x0: xn);
|
||||
SetContext(x0: xn);
|
||||
Opcode(opCmn);
|
||||
Opcode(opCset);
|
||||
Opcode(0xD4200000); // BRK #0
|
||||
Opcode(0xD65F03C0); // RET
|
||||
ExecuteOpcodes();
|
||||
|
||||
|
|
@ -58,10 +55,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
opCset |= ((cond & 15) << 12);
|
||||
|
||||
SetThreadState(x0: wn);
|
||||
SetContext(x0: wn);
|
||||
Opcode(opCmn);
|
||||
Opcode(opCset);
|
||||
Opcode(0xD4200000); // BRK #0
|
||||
Opcode(0xD65F03C0); // RET
|
||||
ExecuteOpcodes();
|
||||
|
||||
|
|
@ -84,10 +80,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
opCset |= ((cond & 15) << 12);
|
||||
|
||||
SetThreadState(x0: xn);
|
||||
SetContext(x0: xn);
|
||||
Opcode(opCmp);
|
||||
Opcode(opCset);
|
||||
Opcode(0xD4200000); // BRK #0
|
||||
Opcode(0xD65F03C0); // RET
|
||||
ExecuteOpcodes();
|
||||
|
||||
|
|
@ -110,10 +105,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
opCset |= ((cond & 15) << 12);
|
||||
|
||||
SetThreadState(x0: wn);
|
||||
SetContext(x0: wn);
|
||||
Opcode(opCmp);
|
||||
Opcode(opCset);
|
||||
Opcode(0xD4200000); // BRK #0
|
||||
Opcode(0xD65F03C0); // RET
|
||||
ExecuteOpcodes();
|
||||
|
||||
|
|
@ -136,11 +130,10 @@ namespace Ryujinx.Tests.Cpu
|
|||
SUB W0, W0, #3
|
||||
MUL W0, W1, W0
|
||||
SDIV W0, W2, W0
|
||||
BRK #0
|
||||
RET
|
||||
*/
|
||||
|
||||
SetThreadState(x0: a);
|
||||
SetContext(x0: a);
|
||||
Opcode(0x11000C02);
|
||||
Opcode(0x51001401);
|
||||
Opcode(0x1B017C42);
|
||||
|
|
@ -148,11 +141,10 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode(0x51000C00);
|
||||
Opcode(0x1B007C20);
|
||||
Opcode(0x1AC00C40);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(GetThreadState().X0, Is.Zero);
|
||||
Assert.That(GetContext().GetX(0), Is.Zero);
|
||||
}
|
||||
|
||||
[Explicit]
|
||||
|
|
@ -185,24 +177,20 @@ namespace Ryujinx.Tests.Cpu
|
|||
FADD S0, S0, S1
|
||||
FDIV S0, S2, S0
|
||||
FMUL S0, S0, S0
|
||||
BRK #0
|
||||
RET
|
||||
*/
|
||||
|
||||
SetThreadState(
|
||||
v0: Sse.SetScalarVector128(a),
|
||||
v1: Sse.SetScalarVector128(b));
|
||||
SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
|
||||
Opcode(0x1E2E1002);
|
||||
Opcode(0x1E201840);
|
||||
Opcode(0x1E211841);
|
||||
Opcode(0x1E212800);
|
||||
Opcode(0x1E201840);
|
||||
Opcode(0x1E200800);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(Sse41.Extract(GetThreadState().V0, (byte)0), Is.EqualTo(16f));
|
||||
Assert.That(GetContext().GetV(0).AsFloat(), Is.EqualTo(16f));
|
||||
}
|
||||
|
||||
[Explicit]
|
||||
|
|
@ -235,24 +223,20 @@ namespace Ryujinx.Tests.Cpu
|
|||
FADD D0, D0, D1
|
||||
FDIV D0, D2, D0
|
||||
FMUL D0, D0, D0
|
||||
BRK #0
|
||||
RET
|
||||
*/
|
||||
|
||||
SetThreadState(
|
||||
v0: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(a)),
|
||||
v1: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(b)));
|
||||
SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
|
||||
Opcode(0x1E6E1002);
|
||||
Opcode(0x1E601840);
|
||||
Opcode(0x1E611841);
|
||||
Opcode(0x1E612800);
|
||||
Opcode(0x1E601840);
|
||||
Opcode(0x1E600800);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(VectorExtractDouble(GetThreadState().V0, (byte)0), Is.EqualTo(16d));
|
||||
Assert.That(GetContext().GetV(0).AsDouble(), Is.EqualTo(16d));
|
||||
}
|
||||
|
||||
[Test, Ignore("The Tester supports only one return point.")]
|
||||
|
|
@ -279,9 +263,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
/*
|
||||
0x0000000000001000: MOV W4, W0
|
||||
0x0000000000001004: CBZ W0, #0x3C
|
||||
0x0000000000001004: CBZ W0, #0x34
|
||||
0x0000000000001008: CMP W0, #1
|
||||
0x000000000000100C: B.LS #0x48
|
||||
0x000000000000100C: B.LS #0x34
|
||||
0x0000000000001010: MOVZ W2, #0x2
|
||||
0x0000000000001014: MOVZ X1, #0x1
|
||||
0x0000000000001018: MOVZ X3, #0
|
||||
|
|
@ -290,22 +274,19 @@ namespace Ryujinx.Tests.Cpu
|
|||
0x0000000000001024: MOV X3, X1
|
||||
0x0000000000001028: MOV X1, X0
|
||||
0x000000000000102C: CMP W4, W2
|
||||
0x0000000000001030: B.HS #0x1C
|
||||
0x0000000000001034: BRK #0
|
||||
0x0000000000001038: RET
|
||||
0x000000000000103C: MOVZ X0, #0
|
||||
0x0000000000001040: BRK #0
|
||||
0x0000000000001030: B.HS #-0x14
|
||||
0x0000000000001034: RET
|
||||
0x0000000000001038: MOVZ X0, #0
|
||||
0x000000000000103C: RET
|
||||
0x0000000000001040: MOVZ X0, #0x1
|
||||
0x0000000000001044: RET
|
||||
0x0000000000001048: MOVZ X0, #0x1
|
||||
0x000000000000104C: BRK #0
|
||||
0x0000000000001050: RET
|
||||
*/
|
||||
|
||||
SetThreadState(x0: a);
|
||||
SetContext(x0: a);
|
||||
Opcode(0x2A0003E4);
|
||||
Opcode(0x340001C0);
|
||||
Opcode(0x340001A0);
|
||||
Opcode(0x7100041F);
|
||||
Opcode(0x540001E9);
|
||||
Opcode(0x540001A9);
|
||||
Opcode(0x52800042);
|
||||
Opcode(0xD2800021);
|
||||
Opcode(0xD2800003);
|
||||
|
|
@ -315,17 +296,14 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode(0xAA0003E1);
|
||||
Opcode(0x6B02009F);
|
||||
Opcode(0x54FFFF62);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
Opcode(0xD2800000);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
Opcode(0xD2800020);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(GetThreadState().X0, Is.EqualTo(Fn(a)));
|
||||
Assert.That(GetContext().GetX(0), Is.EqualTo(Fn(a)));
|
||||
}
|
||||
|
||||
[Explicit]
|
||||
|
|
@ -338,18 +316,16 @@ namespace Ryujinx.Tests.Cpu
|
|||
0x0000000000001000: MOV X0, #2
|
||||
0x0000000000001004: MOV X1, #3
|
||||
0x0000000000001008: ADD X0, X0, X1
|
||||
0x000000000000100C: BRK #0
|
||||
0x0000000000001010: RET
|
||||
0x000000000000100C: RET
|
||||
*/
|
||||
|
||||
Opcode(0xD2800040);
|
||||
Opcode(0xD2800061);
|
||||
Opcode(0x8B010000);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(GetThreadState().X0, Is.EqualTo(result));
|
||||
Assert.That(GetContext().GetX(0), Is.EqualTo(result));
|
||||
|
||||
Reset();
|
||||
|
||||
|
|
@ -357,18 +333,16 @@ namespace Ryujinx.Tests.Cpu
|
|||
0x0000000000001000: MOV X0, #3
|
||||
0x0000000000001004: MOV X1, #2
|
||||
0x0000000000001008: ADD X0, X0, X1
|
||||
0x000000000000100C: BRK #0
|
||||
0x0000000000001010: RET
|
||||
0x000000000000100C: RET
|
||||
*/
|
||||
|
||||
Opcode(0xD2800060);
|
||||
Opcode(0xD2800041);
|
||||
Opcode(0x8B010000);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
|
||||
Assert.That(GetThreadState().X0, Is.EqualTo(result));
|
||||
Assert.That(GetContext().GetX(0), Is.EqualTo(result));
|
||||
}
|
||||
|
||||
[Explicit]
|
||||
|
|
@ -379,9 +353,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
public void SanityCheck(ulong a)
|
||||
{
|
||||
uint opcode = 0xD503201F; // NOP
|
||||
CpuThreadState threadState = SingleOpcode(opcode, x0: a);
|
||||
ExecutionContext context = SingleOpcode(opcode, x0: a);
|
||||
|
||||
Assert.That(threadState.X0, Is.EqualTo(a));
|
||||
Assert.That(context.GetX(0), Is.EqualTo(a));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,11 +1,9 @@
|
|||
// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
|
||||
|
||||
using ChocolArm64.State;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
public class CpuTestSimdCrypto : CpuTest
|
||||
|
|
@ -23,20 +21,20 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint opcode = 0x4E285800; // AESD V0.16B, V0.16B
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
|
||||
Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
|
||||
V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
|
||||
V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
|
||||
|
||||
CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH));
|
||||
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL));
|
||||
Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH));
|
||||
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL));
|
||||
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH));
|
||||
});
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
|
|
@ -55,20 +53,20 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint opcode = 0x4E284800; // AESE V0.16B, V0.16B
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
|
||||
Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
|
||||
V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
|
||||
V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
|
||||
|
||||
CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH));
|
||||
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL));
|
||||
Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH));
|
||||
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL));
|
||||
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH));
|
||||
});
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
|
|
@ -85,24 +83,24 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint opcode = 0x4E287800; // AESIMC V0.16B, V0.16B
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
Vector128<float> v = MakeVectorE0E1(valueL, valueH);
|
||||
V128 v = MakeVectorE0E1(valueL, valueH);
|
||||
|
||||
CpuThreadState threadState = SingleOpcode(
|
||||
ExecutionContext context = SingleOpcode(
|
||||
opcode,
|
||||
v0: rn == 0u ? v : default(Vector128<float>),
|
||||
v1: rn == 1u ? v : default(Vector128<float>));
|
||||
v0: rn == 0u ? v : default(V128),
|
||||
v1: rn == 1u ? v : default(V128));
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH));
|
||||
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
|
||||
});
|
||||
if (rn == 1u)
|
||||
{
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL));
|
||||
Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH));
|
||||
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL));
|
||||
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -120,24 +118,24 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint opcode = 0x4E286800; // AESMC V0.16B, V0.16B
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
Vector128<float> v = MakeVectorE0E1(valueL, valueH);
|
||||
V128 v = MakeVectorE0E1(valueL, valueH);
|
||||
|
||||
CpuThreadState threadState = SingleOpcode(
|
||||
ExecutionContext context = SingleOpcode(
|
||||
opcode,
|
||||
v0: rn == 0u ? v : default(Vector128<float>),
|
||||
v1: rn == 1u ? v : default(Vector128<float>));
|
||||
v0: rn == 0u ? v : default(V128),
|
||||
v1: rn == 1u ? v : default(V128));
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH));
|
||||
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
|
||||
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
|
||||
});
|
||||
if (rn == 1u)
|
||||
{
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL));
|
||||
Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH));
|
||||
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL));
|
||||
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
#define SimdCvt
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -378,7 +379,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -394,7 +395,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -411,7 +412,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -427,7 +428,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -448,7 +449,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -468,7 +469,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (scale << 10);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -489,7 +490,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -509,7 +510,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (scale << 10);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -526,7 +527,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -543,7 +544,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -560,7 +561,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
@ -577,7 +578,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
@ -598,7 +599,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -619,7 +620,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -640,7 +641,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
@ -661,7 +662,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#define SimdExt
|
||||
|
||||
using NUnit.Framework;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -37,9 +37,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0(b);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -61,9 +61,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
V128 v2 = MakeVectorE0E1(b, b);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
#define SimdFcond
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -152,8 +153,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
opcodes |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
|
||||
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0(b);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
bool v = TestContext.CurrentContext.Random.NextBool();
|
||||
bool c = TestContext.CurrentContext.Random.NextBool();
|
||||
|
|
@ -177,8 +178,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
opcodes |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
|
||||
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0(b);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
bool v = TestContext.CurrentContext.Random.NextBool();
|
||||
bool c = TestContext.CurrentContext.Random.NextBool();
|
||||
|
|
@ -202,9 +203,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((cond & 15) << 12);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0(b);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -223,9 +224,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((cond & 15) << 12);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0(b);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#define SimdFmov
|
||||
|
||||
using NUnit.Framework;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((imm8 & 0xFFu) << 13);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -50,7 +50,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((imm8 & 0xFFu) << 13);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
#define SimdImm
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -203,7 +204,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((amount & 1) << 13);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -224,7 +225,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((amount & 3) << 13);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -241,7 +242,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (abc << 16) | (defgh << 5);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -288,7 +289,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -309,7 +310,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -330,7 +331,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -351,7 +352,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
@ -370,7 +371,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (abc << 16) | (defgh << 5);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#define SimdIns
|
||||
|
||||
using NUnit.Framework;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -86,7 +86,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
@ -122,8 +122,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -142,8 +142,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -162,8 +162,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -182,8 +182,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -207,8 +207,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -232,8 +232,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -257,8 +257,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -282,8 +282,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -306,7 +306,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -329,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -352,7 +352,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
|
||||
|
||||
|
|
@ -375,7 +375,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x31: x31, v0: v0);
|
||||
|
||||
|
|
@ -400,8 +400,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -426,8 +426,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -452,8 +452,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -478,8 +478,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
opcode |= (imm4 << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -502,7 +502,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -525,7 +525,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -547,7 +547,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -569,7 +569,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -591,7 +591,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x31: x31, v1: v1);
|
||||
|
||||
|
|
@ -614,7 +614,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -637,7 +637,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -660,7 +660,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
||||
|
||||
|
|
@ -682,7 +682,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcode |= (imm5 << 16);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcode, x31: x31, v1: v1);
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,8 +1,8 @@
|
|||
#define SimdRegElem
|
||||
|
||||
using NUnit.Framework;
|
||||
using ARMeilleure.State;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -95,9 +95,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (m << 20) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -122,9 +122,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -150,9 +150,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (m << 20) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -177,9 +177,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
#define SimdRegElemF
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -230,9 +231,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
opcodes |= (l << 21) | (h << 11);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -255,9 +256,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
opcodes |= h << 11;
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -287,9 +288,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -316,9 +317,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= h << 11;
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -342,9 +343,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (h << 11);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -367,9 +368,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= h << 11;
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE1(z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE1(z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -399,9 +400,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (l << 21) | (h << 11);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
@ -428,9 +429,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= h << 11;
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
Vector128<float> v2 = MakeVectorE0E1(b, b * h);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
V128 v2 = MakeVectorE0E1(b, b * h);
|
||||
|
||||
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
#define SimdShImm
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -488,8 +489,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -509,8 +510,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -532,8 +533,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -553,8 +554,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -574,8 +575,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -597,8 +598,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -620,8 +621,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -643,8 +644,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -664,8 +665,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -687,8 +688,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -710,8 +711,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -733,8 +734,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -754,8 +755,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -777,8 +778,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -800,8 +801,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -823,8 +824,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a * q);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a * q);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -844,8 +845,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -867,8 +868,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -890,8 +891,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -913,8 +914,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(a, a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -934,8 +935,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -955,8 +956,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -976,8 +977,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (immHb << 16);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -999,8 +1000,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -1022,8 +1023,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
@ -1045,8 +1046,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= (immHb << 16);
|
||||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0(a);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
#define SimdTbl
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
|
|
@ -146,9 +147,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(table0, table0);
|
||||
V128 v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
|
|
@ -169,10 +170,10 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(table0, table0);
|
||||
V128 v2 = MakeVectorE0E1(table1, table1);
|
||||
V128 v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
|
|
@ -193,10 +194,10 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(indexes, indexes);
|
||||
V128 v30 = MakeVectorE0E1(z, z);
|
||||
V128 v31 = MakeVectorE0E1(table0, table0);
|
||||
V128 v0 = MakeVectorE0E1(table1, table1);
|
||||
V128 v1 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v30: v30, v31: v31);
|
||||
|
||||
|
|
@ -218,11 +219,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v3 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(table0, table0);
|
||||
V128 v2 = MakeVectorE0E1(table1, table1);
|
||||
V128 v3 = MakeVectorE0E1(table2, table2);
|
||||
V128 v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4);
|
||||
|
||||
|
|
@ -244,11 +245,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v2 = MakeVectorE0E1(indexes, indexes);
|
||||
V128 v30 = MakeVectorE0E1(z, z);
|
||||
V128 v31 = MakeVectorE0E1(table0, table0);
|
||||
V128 v0 = MakeVectorE0E1(table1, table1);
|
||||
V128 v1 = MakeVectorE0E1(table2, table2);
|
||||
V128 v2 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v30: v30, v31: v31);
|
||||
|
||||
|
|
@ -271,12 +272,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v0 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v3 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v4 = MakeVectorE0E1(table3, table3);
|
||||
Vector128<float> v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(table0, table0);
|
||||
V128 v2 = MakeVectorE0E1(table1, table1);
|
||||
V128 v3 = MakeVectorE0E1(table2, table2);
|
||||
V128 v4 = MakeVectorE0E1(table3, table3);
|
||||
V128 v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5);
|
||||
|
||||
|
|
@ -299,12 +300,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
opcodes |= ((q & 1) << 30);
|
||||
|
||||
ulong z = TestContext.CurrentContext.Random.NextULong();
|
||||
Vector128<float> v30 = MakeVectorE0E1(z, z);
|
||||
Vector128<float> v31 = MakeVectorE0E1(table0, table0);
|
||||
Vector128<float> v0 = MakeVectorE0E1(table1, table1);
|
||||
Vector128<float> v1 = MakeVectorE0E1(table2, table2);
|
||||
Vector128<float> v2 = MakeVectorE0E1(table3, table3);
|
||||
Vector128<float> v3 = MakeVectorE0E1(indexes, indexes);
|
||||
V128 v30 = MakeVectorE0E1(z, z);
|
||||
V128 v31 = MakeVectorE0E1(table0, table0);
|
||||
V128 v0 = MakeVectorE0E1(table1, table1);
|
||||
V128 v1 = MakeVectorE0E1(table2, table2);
|
||||
V128 v2 = MakeVectorE0E1(table3, table3);
|
||||
V128 v3 = MakeVectorE0E1(indexes, indexes);
|
||||
|
||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v30: v30, v31: v31);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
<PropertyGroup>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<OutputType>Exe</OutputType>
|
||||
<IsPackable>false</IsPackable>
|
||||
|
||||
|
|
@ -30,12 +30,11 @@
|
|||
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="16.2.0" />
|
||||
<PackageReference Include="NUnit" Version="3.12.0" />
|
||||
<PackageReference Include="NUnit3TestAdapter" Version="3.13.0" />
|
||||
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
|
||||
</ItemGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
||||
<ProjectReference Include="..\Ryujinx.Tests.Unicorn\Ryujinx.Tests.Unicorn.csproj" />
|
||||
<ProjectReference Include="..\ARMeilleure\ARMeilleure.csproj" />
|
||||
</ItemGroup>
|
||||
|
||||
<Target Name="CopyUnicorn" AfterTargets="Build">
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue