Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
This commit is contained in:
riperiperi
GitHub
parent
165e658f02
commit
b1b6f294f2
104 changed files with 9426 additions and 479 deletions
530
Ryujinx.Tests/Cpu/CpuTest32.cs
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530
Ryujinx.Tests/Cpu/CpuTest32.cs
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using NUnit.Framework;
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using Ryujinx.Tests.Unicorn;
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using System;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public class CpuTest32
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{
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private uint _currAddress;
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private long _size;
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private uint _entryPoint;
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private IntPtr _ramPointer;
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private MemoryManager _memory;
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private ExecutionContext _context;
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private Translator _translator;
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private static bool _unicornAvailable;
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private UnicornAArch32 _unicornEmu;
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private bool usingMemory;
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static CpuTest32()
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{
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_unicornAvailable = UnicornAArch32.IsAvailable();
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if (!_unicornAvailable)
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{
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Console.WriteLine("WARNING: Could not find Unicorn.");
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}
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}
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[SetUp]
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public void Setup()
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{
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_currAddress = 0x1000;
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_size = 0x1000;
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_entryPoint = _currAddress;
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_ramPointer = Marshal.AllocHGlobal(new IntPtr(_size * 2));
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_memory = new MemoryManager(_ramPointer, addressSpaceBits: 16, useFlatPageTable: true);
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_memory.Map((long)_currAddress, 0, _size*2);
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_context = new ExecutionContext();
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_context.IsAarch32 = true;
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_translator = new Translator(_memory);
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if (_unicornAvailable)
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{
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_unicornEmu = new UnicornAArch32();
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_unicornEmu.MemoryMap(_currAddress, (ulong)_size, MemoryPermission.READ | MemoryPermission.EXEC);
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_unicornEmu.MemoryMap((ulong)(_currAddress + _size), (ulong)_size, MemoryPermission.READ | MemoryPermission.WRITE);
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_unicornEmu.PC = _entryPoint;
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}
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}
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[TearDown]
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public void Teardown()
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{
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Marshal.FreeHGlobal(_ramPointer);
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_memory = null;
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_context = null;
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_translator = null;
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_unicornEmu = null;
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}
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protected void Reset()
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{
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Teardown();
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Setup();
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}
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protected void Opcode(uint opcode)
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{
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_memory.WriteUInt32((long)_currAddress, opcode);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite32((ulong)_currAddress, opcode);
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}
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_currAddress += 4;
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}
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protected ExecutionContext GetContext() => _context;
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protected void SetContext(uint r0 = 0,
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uint r1 = 0,
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uint r2 = 0,
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uint r3 = 0,
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uint sp = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v14 = default,
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V128 v15 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpscr = 0)
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{
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_context.SetX(0, r0);
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_context.SetX(1, r1);
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_context.SetX(2, r2);
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_context.SetX(3, r3);
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_context.SetX(0xd, sp);
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_context.SetV(0, v0);
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_context.SetV(1, v1);
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_context.SetV(2, v2);
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_context.SetV(3, v3);
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_context.SetV(4, v4);
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_context.SetV(5, v5);
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_context.SetV(14, v14);
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_context.SetV(15, v15);
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_context.SetPstateFlag(PState.VFlag, overflow);
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_context.SetPstateFlag(PState.CFlag, carry);
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_context.SetPstateFlag(PState.ZFlag, zero);
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_context.SetPstateFlag(PState.NFlag, negative);
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_context.Fpsr = FPSR.A32Mask & (FPSR)fpscr;
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_context.Fpcr = FPCR.A32Mask & (FPCR)fpscr;
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if (_unicornAvailable)
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{
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_unicornEmu.R[0] = r0;
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_unicornEmu.R[1] = r1;
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_unicornEmu.R[2] = r2;
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_unicornEmu.R[3] = r3;
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_unicornEmu.SP = sp;
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[14] = V128ToSimdValue(v14);
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_unicornEmu.Q[15] = V128ToSimdValue(v15);
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.Fpscr = fpscr;
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}
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}
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protected void ExecuteOpcodes()
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{
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_translator.Execute(_context, _entryPoint);
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if (_unicornAvailable)
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{
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_unicornEmu.RunForCount((ulong)(_currAddress - _entryPoint - 4) / 4);
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}
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}
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protected ExecutionContext SingleOpcode(uint opcode,
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uint r0 = 0,
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uint r1 = 0,
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uint r2 = 0,
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uint r3 = 0,
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uint sp = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v14 = default,
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V128 v15 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpscr = 0,
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bool copyFpFlags = false)
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{
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Opcode(opcode);
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if (copyFpFlags)
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{
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Opcode(0xeef1fa10);
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}
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Opcode(0xe12fff1e); // BX LR
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SetContext(r0, r1, r2, r3, sp, v0, v1, v2, v3, v4, v5, v14, v15, overflow, carry, zero, negative, fpscr);
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ExecuteOpcodes();
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return GetContext();
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}
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protected void SetWorkingMemory(byte[] data)
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{
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_memory.WriteBytes(0x2000, data);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite((ulong)(0x2000), data);
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}
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usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
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}
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/// <summary>Rounding Mode control field.</summary>
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public enum RMode
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{
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/// <summary>Round to Nearest mode.</summary>
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Rn,
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/// <summary>Round towards Plus Infinity mode.</summary>
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Rp,
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/// <summary>Round towards Minus Infinity mode.</summary>
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Rm,
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/// <summary>Round towards Zero mode.</summary>
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Rz
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};
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/// <summary>Floating-point Control Register.</summary>
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protected enum Fpcr
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{
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/// <summary>Rounding Mode control field.</summary>
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RMode = 22,
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/// <summary>Flush-to-zero mode control bit.</summary>
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Fz = 24,
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/// <summary>Default NaN mode control bit.</summary>
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Dn = 25,
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/// <summary>Alternative half-precision control bit.</summary>
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Ahp = 26
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}
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/// <summary>Floating-point Status Register.</summary>
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[Flags]
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protected enum Fpsr
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{
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None = 0,
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/// <summary>Invalid Operation cumulative floating-point exception bit.</summary>
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Ioc = 1 << 0,
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/// <summary>Divide by Zero cumulative floating-point exception bit.</summary>
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Dzc = 1 << 1,
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/// <summary>Overflow cumulative floating-point exception bit.</summary>
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Ofc = 1 << 2,
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/// <summary>Underflow cumulative floating-point exception bit.</summary>
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Ufc = 1 << 3,
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/// <summary>Inexact cumulative floating-point exception bit.</summary>
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Ixc = 1 << 4,
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/// <summary>Input Denormal cumulative floating-point exception bit.</summary>
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Idc = 1 << 7,
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/// <summary>Cumulative saturation bit.</summary>
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Qc = 1 << 27,
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/// <summary>NZCV flags</summary>
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Nzcv = (1 << 28) | (1 << 29) | (1 << 30) | (1 << 31)
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}
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[Flags]
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protected enum FpSkips
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{
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None = 0,
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IfNaNS = 1,
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IfNaND = 2,
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IfUnderflow = 4,
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IfOverflow = 8
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}
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protected enum FpTolerances
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{
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None,
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UpToOneUlpsS,
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UpToOneUlpsD
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}
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protected void CompareAgainstUnicorn(
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Fpsr fpsrMask = Fpsr.None,
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FpSkips fpSkips = FpSkips.None,
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FpTolerances fpTolerances = FpTolerances.None)
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{
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if (!_unicornAvailable)
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{
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return;
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}
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if (fpSkips != FpSkips.None)
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{
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ManageFpSkips(fpSkips);
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}
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Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.R[0]));
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Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.R[1]));
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Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.R[2]));
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Assert.That(_context.GetX(3), Is.EqualTo(_unicornEmu.R[3]));
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Assert.That(_context.GetX(4), Is.EqualTo(_unicornEmu.R[4]));
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Assert.That(_context.GetX(5), Is.EqualTo(_unicornEmu.R[5]));
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Assert.That(_context.GetX(6), Is.EqualTo(_unicornEmu.R[6]));
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Assert.That(_context.GetX(7), Is.EqualTo(_unicornEmu.R[7]));
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Assert.That(_context.GetX(8), Is.EqualTo(_unicornEmu.R[8]));
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Assert.That(_context.GetX(9), Is.EqualTo(_unicornEmu.R[9]));
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Assert.That(_context.GetX(10), Is.EqualTo(_unicornEmu.R[10]));
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Assert.That(_context.GetX(11), Is.EqualTo(_unicornEmu.R[11]));
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Assert.That(_context.GetX(12), Is.EqualTo(_unicornEmu.R[12]));
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Assert.That(_context.GetX(13), Is.EqualTo(_unicornEmu.R[13]));
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Assert.That(_context.GetX(14), Is.EqualTo(_unicornEmu.R[14]));
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if (fpTolerances == FpTolerances.None)
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{
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Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
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}
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else
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{
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ManageFpTolerances(fpTolerances);
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}
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Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]));
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Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]));
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Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]));
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Assert.That(V128ToSimdValue(_context.GetV(4)), Is.EqualTo(_unicornEmu.Q[4]));
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Assert.That(V128ToSimdValue(_context.GetV(5)), Is.EqualTo(_unicornEmu.Q[5]));
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Assert.That(V128ToSimdValue(_context.GetV(6)), Is.EqualTo(_unicornEmu.Q[6]));
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Assert.That(V128ToSimdValue(_context.GetV(7)), Is.EqualTo(_unicornEmu.Q[7]));
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Assert.That(V128ToSimdValue(_context.GetV(8)), Is.EqualTo(_unicornEmu.Q[8]));
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Assert.That(V128ToSimdValue(_context.GetV(9)), Is.EqualTo(_unicornEmu.Q[9]));
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Assert.That(V128ToSimdValue(_context.GetV(10)), Is.EqualTo(_unicornEmu.Q[10]));
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Assert.That(V128ToSimdValue(_context.GetV(11)), Is.EqualTo(_unicornEmu.Q[11]));
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Assert.That(V128ToSimdValue(_context.GetV(12)), Is.EqualTo(_unicornEmu.Q[12]));
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Assert.That(V128ToSimdValue(_context.GetV(13)), Is.EqualTo(_unicornEmu.Q[13]));
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Assert.That(V128ToSimdValue(_context.GetV(14)), Is.EqualTo(_unicornEmu.Q[14]));
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Assert.That(V128ToSimdValue(_context.GetV(15)), Is.EqualTo(_unicornEmu.Q[15]));
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Assert.That((int)_context.Fpcr | ((int)_context.Fpsr & (int)fpsrMask), Is.EqualTo(_unicornEmu.Fpscr));
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Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag));
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Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag));
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Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag));
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Assert.That(_context.GetPstateFlag(PState.NFlag), Is.EqualTo(_unicornEmu.NegativeFlag));
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|
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if (usingMemory)
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{
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byte[] meilleureMem = _memory.ReadBytes((long)(0x2000), _size);
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byte[] unicornMem = _unicornEmu.MemoryRead((ulong)(0x2000), (ulong)_size);
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|
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for (int i = 0; i < _size; i++)
|
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{
|
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Assert.AreEqual(meilleureMem[i], unicornMem[i]);
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}
|
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}
|
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}
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|
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private void ManageFpSkips(FpSkips fpSkips)
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{
|
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if (fpSkips.HasFlag(FpSkips.IfNaNS))
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{
|
||||
if (float.IsNaN(_unicornEmu.Q[0].AsFloat()))
|
||||
{
|
||||
Assert.Ignore("NaN test.");
|
||||
}
|
||||
}
|
||||
else if (fpSkips.HasFlag(FpSkips.IfNaND))
|
||||
{
|
||||
if (double.IsNaN(_unicornEmu.Q[0].AsDouble()))
|
||||
{
|
||||
Assert.Ignore("NaN test.");
|
||||
}
|
||||
}
|
||||
|
||||
if (fpSkips.HasFlag(FpSkips.IfUnderflow))
|
||||
{
|
||||
if ((_unicornEmu.Fpscr & (int)Fpsr.Ufc) != 0)
|
||||
{
|
||||
Assert.Ignore("Underflow test.");
|
||||
}
|
||||
}
|
||||
|
||||
if (fpSkips.HasFlag(FpSkips.IfOverflow))
|
||||
{
|
||||
if ((_unicornEmu.Fpscr & (int)Fpsr.Ofc) != 0)
|
||||
{
|
||||
Assert.Ignore("Overflow test.");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private void ManageFpTolerances(FpTolerances fpTolerances)
|
||||
{
|
||||
bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
|
||||
bool IsNormalOrSubnormalD(double d) => double.IsNormal(d) || double.IsSubnormal(d);
|
||||
|
||||
if (!Is.EqualTo(_unicornEmu.Q[0]).ApplyTo(V128ToSimdValue(_context.GetV(0))).IsSuccess)
|
||||
{
|
||||
if (fpTolerances == FpTolerances.UpToOneUlpsS)
|
||||
{
|
||||
if (IsNormalOrSubnormalS(_unicornEmu.Q[0].AsFloat()) &&
|
||||
IsNormalOrSubnormalS(_context.GetV(0).AsFloat()))
|
||||
{
|
||||
Assert.That(_context.GetV(0).GetFloat(0),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps);
|
||||
Assert.That(_context.GetV(0).GetFloat(1),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps);
|
||||
Assert.That(_context.GetV(0).GetFloat(2),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps);
|
||||
Assert.That(_context.GetV(0).GetFloat(3),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps);
|
||||
|
||||
Console.WriteLine(fpTolerances);
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
|
||||
}
|
||||
}
|
||||
|
||||
if (fpTolerances == FpTolerances.UpToOneUlpsD)
|
||||
{
|
||||
if (IsNormalOrSubnormalD(_unicornEmu.Q[0].AsDouble()) &&
|
||||
IsNormalOrSubnormalD(_context.GetV(0).AsDouble()))
|
||||
{
|
||||
Assert.That(_context.GetV(0).GetDouble(0),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps);
|
||||
Assert.That(_context.GetV(0).GetDouble(1),
|
||||
Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps);
|
||||
|
||||
Console.WriteLine(fpTolerances);
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private static SimdValue V128ToSimdValue(V128 value)
|
||||
{
|
||||
return new SimdValue(value.GetUInt64(0), value.GetUInt64(1));
|
||||
}
|
||||
|
||||
protected static V128 MakeVectorScalar(float value) => new V128(value);
|
||||
protected static V128 MakeVectorScalar(double value) => new V128(value);
|
||||
|
||||
protected static V128 MakeVectorE0(ulong e0) => new V128(e0, 0);
|
||||
protected static V128 MakeVectorE1(ulong e1) => new V128(0, e1);
|
||||
|
||||
protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new V128(e0, e1);
|
||||
|
||||
protected static ulong GetVectorE0(V128 vector) => vector.GetUInt64(0);
|
||||
protected static ulong GetVectorE1(V128 vector) => vector.GetUInt64(1);
|
||||
|
||||
protected static ushort GenNormalH()
|
||||
{
|
||||
uint rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextUShort();
|
||||
while ((rnd & 0x7C00u) == 0u ||
|
||||
(~rnd & 0x7C00u) == 0u);
|
||||
|
||||
return (ushort)rnd;
|
||||
}
|
||||
|
||||
protected static ushort GenSubnormalH()
|
||||
{
|
||||
uint rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextUShort();
|
||||
while ((rnd & 0x03FFu) == 0u);
|
||||
|
||||
return (ushort)(rnd & 0x83FFu);
|
||||
}
|
||||
|
||||
protected static uint GenNormalS()
|
||||
{
|
||||
uint rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextUInt();
|
||||
while ((rnd & 0x7F800000u) == 0u ||
|
||||
(~rnd & 0x7F800000u) == 0u);
|
||||
|
||||
return rnd;
|
||||
}
|
||||
|
||||
protected static uint GenSubnormalS()
|
||||
{
|
||||
uint rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextUInt();
|
||||
while ((rnd & 0x007FFFFFu) == 0u);
|
||||
|
||||
return rnd & 0x807FFFFFu;
|
||||
}
|
||||
|
||||
protected static ulong GenNormalD()
|
||||
{
|
||||
ulong rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextULong();
|
||||
while ((rnd & 0x7FF0000000000000ul) == 0ul ||
|
||||
(~rnd & 0x7FF0000000000000ul) == 0ul);
|
||||
|
||||
return rnd;
|
||||
}
|
||||
|
||||
protected static ulong GenSubnormalD()
|
||||
{
|
||||
ulong rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextULong();
|
||||
while ((rnd & 0x000FFFFFFFFFFFFFul) == 0ul);
|
||||
|
||||
return rnd & 0x800FFFFFFFFFFFFFul;
|
||||
}
|
||||
}
|
||||
}
|
||||
61
Ryujinx.Tests/Cpu/CpuTestAlu32.cs
Normal file
61
Ryujinx.Tests/Cpu/CpuTestAlu32.cs
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#define Alu32
|
||||
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("Alu32")]
|
||||
public sealed class CpuTestAlu32 : CpuTest32
|
||||
{
|
||||
#if Alu32
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Lsr_Lsl_Asr_Ror_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xe1b00030u, // LSRS R0, R0, R0
|
||||
0xe1b00010u, // LSLS R0, R0, R0
|
||||
0xe1b00050u, // ASRS R0, R0, R0
|
||||
0xe1b00070u // RORS R0, R0, R0
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("RBIT <Rd>, <Rn>")]
|
||||
public void Rbit_32bit([Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
|
||||
{
|
||||
uint opcode = 0xe6ff0f30u; // RBIT R0, R0
|
||||
opcode |= ((rm & 15) << 0) | ((rd & 15) << 12);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r1: wn, sp: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Lsr_Lsl_Asr_Ror([ValueSource("_Lsr_Lsl_Asr_Ror_")] uint opcode,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
|
||||
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
|
||||
{
|
||||
uint rd = 0;
|
||||
uint rm = 1;
|
||||
uint rs = 2;
|
||||
opcode |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rs & 15) << 8);
|
||||
|
||||
SingleOpcode(opcode, r1: shiftValue, r2: (uint)shiftAmount);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
84
Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
Normal file
84
Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
#define AluRs32
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("AluRs32")]
|
||||
public sealed class CpuTestAluRs32 : CpuTest32
|
||||
{
|
||||
#if AluRs32
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Add_Adds_Rsb_Rsbs_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xe0800000u, // ADD R0, R0, R0, LSL #0
|
||||
0xe0900000u, // ADDS R0, R0, R0, LSL #0
|
||||
0xe0600000u, // RSB R0, R0, R0, LSL #0
|
||||
0xe0700000u // RSBS R0, R0, R0, LSL #0
|
||||
};
|
||||
}
|
||||
|
||||
private static uint[] _Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xe0a00000u, // ADC R0, R0, R0
|
||||
0xe0b00000u, // ADCS R0, R0, R0
|
||||
0xe0e00000u, // RSC R0, R0, R0
|
||||
0xe0f00000u, // RSCS R0, R0, R0
|
||||
0xe0c00000u, // SBC R0, R0, R0
|
||||
0xe0d00000u // SBCS R0, R0, R0
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntAmount = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource("_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_")] uint opcode,
|
||||
[Values(0u, 13u)] uint rd,
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Values(2u, 13u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r1: wn, r2: wm, sp: sp, carry: carryIn);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Add_Adds_Rsb_Rsbs([ValueSource("_Add_Adds_Rsb_Rsbs_")] uint opcode,
|
||||
[Values(0u, 13u)] uint rd,
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Values(2u, 13u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
{
|
||||
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
|
||||
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r1: wn, r2: wm, sp: sp);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
108
Ryujinx.Tests/Cpu/CpuTestBf32.cs
Normal file
108
Ryujinx.Tests/Cpu/CpuTestBf32.cs
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
#define Bf32
|
||||
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("Bf32")]
|
||||
public sealed class CpuTestBf32 : CpuTest32
|
||||
{
|
||||
#if Bf32
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImmr = 2;
|
||||
private const int RndCntImms = 2;
|
||||
|
||||
[Test, Pairwise, Description("BFC <Rd>, #<lsb>, #<width>")]
|
||||
public void Bfc([Values(0u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wd,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
|
||||
{
|
||||
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
|
||||
uint opcode = 0xe7c0001fu; // BFC R0, #0, #1
|
||||
opcode |= ((rd & 0xf) << 12);
|
||||
opcode |= ((msb & 31) << 16) | ((lsb & 31) << 7);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r0: wd, sp: sp);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("BFI <Rd>, <Rn>, #<lsb>, #<width>")]
|
||||
public void Bfi([Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
|
||||
{
|
||||
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
|
||||
uint opcode = 0xe7c00010u; // BFI R0, R0, #0, #1
|
||||
opcode |= ((rd & 0xf) << 12);
|
||||
opcode |= ((rn & 0xf) << 0);
|
||||
opcode |= ((msb & 31) << 16) | ((lsb & 31) << 7);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r0: wd, r1: wn, sp: sp);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UBFX <Rd>, <Rn>, #<lsb>, #<width>")]
|
||||
public void Ubfx([Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
|
||||
{
|
||||
if (lsb + widthm1 > 31)
|
||||
{
|
||||
widthm1 -= (lsb + widthm1) - 31;
|
||||
}
|
||||
uint opcode = 0xe7e00050u; // UBFX R0, R0, #0, #1
|
||||
opcode |= ((rd & 0xf) << 12);
|
||||
opcode |= ((rn & 0xf) << 0);
|
||||
opcode |= ((widthm1 & 31) << 16) | ((lsb & 31) << 7);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r0: wd, r1: wn, sp: sp);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SBFX <Rd>, <Rn>, #<lsb>, #<width>")]
|
||||
public void Sbfx([Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
|
||||
{
|
||||
if (lsb + widthm1 > 31)
|
||||
{
|
||||
widthm1 -= (lsb + widthm1) - 31;
|
||||
}
|
||||
uint opcode = 0xe7a00050u; // SBFX R0, R0, #0, #1
|
||||
opcode |= ((rd & 0xf) << 12);
|
||||
opcode |= ((rn & 0xf) << 0);
|
||||
opcode |= ((widthm1 & 31) << 16) | ((lsb & 31) << 7);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r0: wd, r1: wn, sp: sp);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
61
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
Normal file
61
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#define SimdLogical32
|
||||
|
||||
using ARMeilleure.State;
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("SimdLogical32")]
|
||||
public sealed class CpuTestSimdLogical32 : CpuTest32
|
||||
{
|
||||
#if SimdLogical32
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vbif_Vbit_Vbsl_Vand_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xf3300110u, // VBIF D0, D0, D0
|
||||
0xf3200110u, // VBIT D0, D0, D0
|
||||
0xf3100110u, // VBSL D0, D0, D0
|
||||
0xf2000110u // VAND D0, D0, D0
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vbif_Vbit_Vbsl_Vand([ValueSource("_Vbif_Vbit_Vbsl_Vand_")] uint opcode,
|
||||
[Range(0u, 4u)] uint rd,
|
||||
[Range(0u, 4u)] uint rn,
|
||||
[Range(0u, 4u)] uint rm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
[Values] bool q)
|
||||
{
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rn <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
319
Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
Normal file
319
Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
Normal file
|
|
@ -0,0 +1,319 @@
|
|||
#define SimdMemory32
|
||||
|
||||
using ARMeilleure.State;
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("SimdMemory32")]
|
||||
public sealed class CpuTestSimdMemory32 : CpuTest32
|
||||
{
|
||||
#if SimdMemory32
|
||||
private const int RndCntImm = 2;
|
||||
|
||||
private uint[] LDSTModes =
|
||||
{
|
||||
// LD1
|
||||
0b0111,
|
||||
0b1010,
|
||||
0b0110,
|
||||
0b0010,
|
||||
|
||||
// LD2
|
||||
0b1000,
|
||||
0b1001,
|
||||
0b0011,
|
||||
|
||||
// LD3
|
||||
0b0100,
|
||||
0b0101,
|
||||
|
||||
// LD4
|
||||
0b0000,
|
||||
0b0001
|
||||
};
|
||||
|
||||
[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (single n element structure)")]
|
||||
public void Vldn_Single([Values(0u, 1u, 2u)] uint size,
|
||||
[Values(0u, 13u)] uint rn,
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
|
||||
|
||||
opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
|
||||
|
||||
uint index_align = (index << (int)(1 + size)) & 15;
|
||||
|
||||
opcode |= (index_align) << 4;
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (all lanes)")]
|
||||
public void Vldn_All([Values(0u, 13u)] uint rn,
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Range(0u, 2u)] uint size,
|
||||
[Values] bool t,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
|
||||
|
||||
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
|
||||
if (t) opcode |= 1 << 5;
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
|
||||
public void Vldn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Values(0u, 13u)] uint rn,
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 3u)] uint mode,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
|
||||
|
||||
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (single n element structure)")]
|
||||
public void Vstn_Single([Values(0u, 1u, 2u)] uint size,
|
||||
[Values(0u, 13u)] uint rn,
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
|
||||
|
||||
uint opcode = 0xf4800000u; // VST1.8 {D0[0]}, [R0], R0
|
||||
|
||||
opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
|
||||
|
||||
uint index_align = (index << (int)(1 + size)) & 15;
|
||||
|
||||
opcode |= (index_align) << 4;
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc.
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
|
||||
public void Vstn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Values(0u, 13u)] uint rn,
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 3u)] uint mode,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
|
||||
|
||||
uint opcode = 0xf4000000u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
|
||||
|
||||
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VLDM.<size> <Rn>{!}, <d/sreglist>")]
|
||||
public void Vldm([Values(0u, 13u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 2u)] uint mode,
|
||||
[Values(0x1u, 0x32u)] [Random(2u, 31u, RndCntImm)] uint regs,
|
||||
[Values] bool single)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
|
||||
|
||||
uint[] vldmModes = {
|
||||
// Note: 3rd 0 leaves a space for "D".
|
||||
0b0100, // Increment after.
|
||||
0b0101, // Increment after. (!)
|
||||
0b1001 // Decrement before. (!)
|
||||
};
|
||||
|
||||
opcode |= ((vldmModes[mode] & 15) << 21);
|
||||
opcode |= ((rn & 15) << 16);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
opcode |= ((uint)(single ? 0 : 1) << 8);
|
||||
|
||||
if (!single) regs = (regs << 1); // Low bit must be 0 - must be even number of registers.
|
||||
uint regSize = single ? 1u : 2u;
|
||||
|
||||
if (vd + (regs / regSize) > 32) // Can't address further than S31 or D31.
|
||||
{
|
||||
regs -= (vd + (regs / regSize)) - 32;
|
||||
}
|
||||
|
||||
if (regs / regSize > 16) // Can't do more than 16 registers at a time.
|
||||
{
|
||||
regs = 16 * regSize;
|
||||
}
|
||||
|
||||
opcode |= regs & 0xff;
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, sp: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VLDR.<size> <Sd>, [<Rn> {, #{+/-}<imm>}]")]
|
||||
public void Vldr([Values(2u, 3u)] uint size, // FP16 is not supported for now
|
||||
[Values(0u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values] bool sub)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
|
||||
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
|
||||
|
||||
if (sub)
|
||||
{
|
||||
opcode &= ~(uint)(1 << 23);
|
||||
}
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
opcode |= ((sd & 0x1) << 22);
|
||||
opcode |= ((sd & 0x1e) << 11);
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode |= ((sd & 0x10) << 18);
|
||||
opcode |= ((sd & 0xf) << 12);
|
||||
}
|
||||
opcode |= imm & 0xff;
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSTR.<size> <Sd>, [<Rn> {, #{+/-}<imm>}]")]
|
||||
public void Vstr([Values(2u, 3u)] uint size, // FP16 is not supported for now
|
||||
[Values(0u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values] bool sub)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(data);
|
||||
|
||||
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
|
||||
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
|
||||
|
||||
if (sub)
|
||||
{
|
||||
opcode &= ~(uint)(1 << 23);
|
||||
}
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
opcode |= ((sd & 0x1) << 22);
|
||||
opcode |= ((sd & 0x1e) << 11);
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode |= ((sd & 0x10) << 18);
|
||||
opcode |= ((sd & 0xf) << 12);
|
||||
}
|
||||
opcode |= imm & 0xff;
|
||||
|
||||
(V128 vec1, V128 vec2, _, _) = GenerateTestVectors();
|
||||
|
||||
SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
private (V128, V128, V128, V128) GenerateTestVectors()
|
||||
{
|
||||
return (
|
||||
new V128(-12.43f, 1872.23f, 4456.23f, -5622.2f),
|
||||
new V128(0.0f, float.NaN, float.PositiveInfinity, float.NegativeInfinity),
|
||||
new V128(1.23e10f, -0.0f, -0.123f, 0.123f),
|
||||
new V128(float.Epsilon, 3.5f, 925.23f, -104.9f)
|
||||
);
|
||||
}
|
||||
|
||||
private byte[] GenerateVectorSequence(int length)
|
||||
{
|
||||
int floatLength = length >> 2;
|
||||
float[] data = new float[floatLength];
|
||||
|
||||
for (int i = 0; i < floatLength; i++)
|
||||
{
|
||||
data[i] = i + (i / 9f);
|
||||
}
|
||||
|
||||
var result = new byte[length];
|
||||
Buffer.BlockCopy(data, 0, result, 0, result.Length);
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
494
Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs
Normal file
494
Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs
Normal file
|
|
@ -0,0 +1,494 @@
|
|||
#define SimdMov32
|
||||
|
||||
using ARMeilleure.State;
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("SimdMov32")]
|
||||
public sealed class CpuTestSimdMov32 : CpuTest32
|
||||
{
|
||||
#if SimdMov32
|
||||
private const int RndCntImm = 2;
|
||||
|
||||
[Test, Pairwise, Description("VMOV.I<size> <Dd/Qd>, #<imm>")]
|
||||
public void Movi_V([Range(0u, 10u)] uint variant,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0x0u)] [Random(1u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint[] variants =
|
||||
{
|
||||
// I32
|
||||
0b0000_0,
|
||||
0b0010_0,
|
||||
0b0100_0,
|
||||
0b0110_0,
|
||||
|
||||
// I16
|
||||
0b1000_0,
|
||||
0b1010_0,
|
||||
|
||||
// DT
|
||||
0b1100_0,
|
||||
0b1101_0,
|
||||
0b1110_0,
|
||||
0b1111_0,
|
||||
|
||||
0b1110_1
|
||||
};
|
||||
|
||||
|
||||
uint opcode = 0xf2800010u; // VMOV.I32 D0, #0
|
||||
uint cmodeOp = variants[variant];
|
||||
|
||||
if (q)
|
||||
{
|
||||
vd <<= 1;
|
||||
}
|
||||
|
||||
opcode |= ((cmodeOp & 1) << 5) | ((cmodeOp & 0x1e) << 7);
|
||||
opcode |= ((q ? 1u : 0u) << 6);
|
||||
opcode |= (imm & 0xf) | ((imm & 0x70) << 12) | ((imm & 0x80) << 16);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
SingleOpcode(opcode);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VMOV.F<size> <Sd>, #<imm>")]
|
||||
public void Movi_S([Range(2u, 3u)] uint size,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm)
|
||||
{
|
||||
uint opcode = 0xeeb00800u;
|
||||
opcode |= (size & 3) << 8;
|
||||
opcode |= (imm & 0xf) | ((imm & 0xf0) << 12);
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
opcode |= ((vd & 0x1) << 22);
|
||||
opcode |= ((vd & 0x1e) << 11);
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
}
|
||||
|
||||
SingleOpcode(opcode);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VMOV <Rd>, <Sd>")]
|
||||
public void Mov_GP([Values(0u, 1u, 2u, 3u)] uint vn,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt,
|
||||
[Random(RndCntImm)] uint valueRn,
|
||||
[Random(RndCntImm)] ulong valueVn1,
|
||||
[Random(RndCntImm)] ulong valueVn2,
|
||||
[Values] bool op)
|
||||
{
|
||||
uint opcode = 0xee000a10u; // VMOV S0, R0
|
||||
opcode |= (vn & 1) << 7;
|
||||
opcode |= (vn & 0x1e) << 15;
|
||||
opcode |= (rt & 0xf) << 12;
|
||||
|
||||
if (op) opcode |= 1 << 20;
|
||||
|
||||
SingleOpcode(opcode, r0: valueRn, r1: valueRn, r2: valueRn, r3: valueRn, v0: new V128(valueVn1, valueVn2));
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VMOV.<size> <Rt>, <Dn[x]>")]
|
||||
public void Mov_GP_Elem([Range(0u, 7u)] uint vn,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt,
|
||||
[Range(0u, 2u)] uint size,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Random(1)] uint valueRn,
|
||||
[Random(1)] ulong valueVn1,
|
||||
[Random(1)] ulong valueVn2,
|
||||
[Values] bool op,
|
||||
[Values] bool u)
|
||||
{
|
||||
uint opcode = 0xee000b10u; // VMOV.32 D0[0], R0
|
||||
|
||||
uint opEncode = 0b01000;
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
opEncode = (0b1000) | index & 7;
|
||||
break;
|
||||
case 1:
|
||||
opEncode = (0b0001) | ((index & 3) << 1);
|
||||
break;
|
||||
case 2:
|
||||
opEncode = (index & 1) << 2;
|
||||
break;
|
||||
}
|
||||
|
||||
opcode |= ((opEncode >> 2) << 21) | ((opEncode & 3) << 5);
|
||||
|
||||
opcode |= (vn & 0x10) << 3;
|
||||
opcode |= (vn & 0xf) << 16;
|
||||
opcode |= (rt & 0xf) << 12;
|
||||
|
||||
if (op)
|
||||
{
|
||||
opcode |= 1 << 20;
|
||||
if (u && size != 2)
|
||||
{
|
||||
opcode |= 1 << 23;
|
||||
}
|
||||
}
|
||||
|
||||
SingleOpcode(opcode, r0: valueRn, r1: valueRn, r2: valueRn, r3: valueRn, v0: new V128(valueVn1, valueVn2), v1: new V128(valueVn2, valueVn1));
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("(VMOV <Rt>, <Rt2>, <Dm>), (VMOV <Dm>, <Rt>, <Rt2>)")]
|
||||
public void Mov_GP_D([Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt2,
|
||||
[Random(RndCntImm)] uint valueRt1,
|
||||
[Random(RndCntImm)] uint valueRt2,
|
||||
[Random(RndCntImm)] ulong valueVn1,
|
||||
[Random(RndCntImm)] ulong valueVn2,
|
||||
[Values] bool op)
|
||||
{
|
||||
uint opcode = 0xec400b10u; // VMOV D0, R0, R0
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (rt & 0xf) << 12;
|
||||
opcode |= (rt2 & 0xf) << 16;
|
||||
|
||||
if (op)
|
||||
{
|
||||
opcode |= 1 << 20;
|
||||
}
|
||||
|
||||
SingleOpcode(opcode, r0: valueRt1, r1: valueRt2, r2: valueRt1, r3: valueRt2, v0: new V128(valueVn1, valueVn2));
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("(VMOV <Rt>, <Rt2>, <Sm>, <Sm1>), (VMOV <Sm>, <Sm1>, <Rt>, <Rt2>)")]
|
||||
public void Mov_GP_2([Range(0u, 7u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt2,
|
||||
[Random(RndCntImm)] uint valueRt1,
|
||||
[Random(RndCntImm)] uint valueRt2,
|
||||
[Random(RndCntImm)] ulong valueVn1,
|
||||
[Random(RndCntImm)] ulong valueVn2,
|
||||
[Values] bool op)
|
||||
{
|
||||
uint opcode = 0xec400a10u; // VMOV S0, S1, R0, R0
|
||||
opcode |= (vm & 1) << 5;
|
||||
opcode |= (vm & 0x1e) >> 1;
|
||||
opcode |= (rt & 0xf) << 12;
|
||||
opcode |= (rt2 & 0xf) << 16;
|
||||
|
||||
if (op)
|
||||
{
|
||||
opcode |= 1 << 20;
|
||||
}
|
||||
|
||||
SingleOpcode(opcode, r0: valueRt1, r1: valueRt2, r2: valueRt1, r3: valueRt2, v0: new V128(valueVn1, valueVn2), v1: new V128(valueVn2, valueVn1));
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VMOVN.<size> <Dt>, <Qm>")]
|
||||
public void Movn_V([Range(0u, 1u, 2u)] uint size,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 2u, 4u, 8u)] uint vm)
|
||||
{
|
||||
uint opcode = 0xf3b20200u; // VMOVN.I16 D0, Q0
|
||||
|
||||
opcode |= (size & 0x3) << 18;
|
||||
opcode |= ((vm & 0x10) << 1);
|
||||
opcode |= ((vm & 0xf) << 0);
|
||||
|
||||
opcode |= ((vd & 0x10) << 18);
|
||||
opcode |= ((vd & 0xf) << 12);
|
||||
|
||||
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VTRN.<size> <Vd>, <Vm>")]
|
||||
public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf3b20080u; // VTRN.8 D0, D0
|
||||
if (vm == vd)
|
||||
{
|
||||
return; // Undefined.
|
||||
}
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
vd <<= 1; vm <<= 1;
|
||||
}
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
opcode |= (size & 0x3) << 18;
|
||||
|
||||
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VZIP.<size> <Vd>, <Vm>")]
|
||||
public void Vzip([Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf3b20180u; // VZIP.8 D0, D0
|
||||
if (vm == vd || (size == 2 && !q))
|
||||
{
|
||||
return; // Undefined.
|
||||
}
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
vd <<= 1; vm <<= 1;
|
||||
}
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
opcode |= (size & 0x3) << 18;
|
||||
|
||||
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VUZP.<size> <Vd>, <Vm>")]
|
||||
public void Vuzp([Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf3b20100u; // VUZP.8 d0, d0
|
||||
if (vm == vd || (size == 2 && !q))
|
||||
{
|
||||
return; // Undefined.
|
||||
}
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
vd <<= 1; vm <<= 1;
|
||||
}
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
opcode |= (size & 0x3) << 18;
|
||||
|
||||
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VTBL.8 <Dd>, {list}, <Dm>")]
|
||||
public void Vtbl([Range(0u, 6u)] uint vm, // Indices, include potentially invalid.
|
||||
[Range(4u, 12u)] uint vn, // Selection.
|
||||
[Values(0u, 1u)] uint vd, // Destinations.
|
||||
[Range(0u, 3u)] uint length,
|
||||
[Values] bool x)
|
||||
{
|
||||
uint opcode = 0xf3b00800u; // VTBL.8 D0, {D0}, D0
|
||||
if (vn + length > 31)
|
||||
{
|
||||
return; // Undefined.
|
||||
}
|
||||
|
||||
if (x)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
}
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
|
||||
opcode |= (vn & 0x10) << 3;
|
||||
opcode |= (vn & 0xf) << 16;
|
||||
opcode |= (length & 0x3) << 8;
|
||||
|
||||
var rnd = TestContext.CurrentContext.Random;
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v4 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v5 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
byte maxIndex = (byte)(length * 8 - 1);
|
||||
byte[] b0 = new byte[16];
|
||||
byte[] b1 = new byte[16];
|
||||
for (int i=0; i<16; i++)
|
||||
{
|
||||
b0[i] = rnd.NextByte(maxIndex);
|
||||
b1[i] = rnd.NextByte(maxIndex);
|
||||
}
|
||||
|
||||
V128 v0 = new V128(b0);
|
||||
V128 v1 = new V128(b1);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VEXT.8 {<Vd>,} <Vn>, <Vm>, #<imm>")]
|
||||
public void Vext([Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vn,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 15u)] uint imm4,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2b00000; // VEXT.32 D0, D0, D0, #0
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
vd <<= 1; vm <<= 1; vn <<= 1;
|
||||
}
|
||||
else if (imm4 > 7)
|
||||
{
|
||||
return; // Undefined.
|
||||
}
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
opcode |= (vn & 0x10) << 3;
|
||||
opcode |= (vn & 0xf) << 16;
|
||||
opcode |= (imm4 & 0xf) << 8;
|
||||
|
||||
V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VDUP.<size> <Vd>, <Rt>")]
|
||||
public void Vdup_GP([Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rt,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Random(RndCntImm)] uint valueRn,
|
||||
[Random(RndCntImm)] ulong valueVn1,
|
||||
[Random(RndCntImm)] ulong valueVn2,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xee800b10; // VDUP.32 d0, r0
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 21;
|
||||
vd <<= 1;
|
||||
}
|
||||
|
||||
opcode |= (vd & 0x10) << 3;
|
||||
opcode |= (vd & 0xf) << 16;
|
||||
opcode |= (rt & 0xf) << 12;
|
||||
|
||||
opcode |= (size & 1) << 5; // E
|
||||
opcode |= (size & 2) << 21; // B
|
||||
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, r0: valueRn, r1: valueRn, r2: valueRn, r3: valueRn, v0: new V128(valueVn1, valueVn2), v1: v1);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VDUP.<size> <Vd>, <Dm[x]>")]
|
||||
public void Vdup_S([Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vm,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Random(RndCntImm)] ulong valueVn1,
|
||||
[Random(RndCntImm)] ulong valueVn2,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf3b00c00;
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
vd <<= 1;
|
||||
}
|
||||
|
||||
opcode |= (vd & 0x10) << 18;
|
||||
opcode |= (vd & 0xf) << 12;
|
||||
opcode |= (vm & 0x10) << 1;
|
||||
opcode |= (vm & 0xf);
|
||||
|
||||
uint imm4 = 0;
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
imm4 |= 0b0100 | ((index & 1) << 3);
|
||||
break;
|
||||
case 1:
|
||||
imm4 |= 0b0010 | ((index & 3) << 2);
|
||||
break;
|
||||
case 2:
|
||||
imm4 |= 0b0001 | ((index & 7) << 1);
|
||||
break;
|
||||
}
|
||||
|
||||
opcode |= imm4 << 16;
|
||||
|
||||
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
SingleOpcode(opcode, v0: new V128(valueVn1, valueVn2), v1: v1, v2: v2, v3: v3);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
351
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
Normal file
351
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
#define SimdReg32
|
||||
|
||||
using ARMeilleure.State;
|
||||
using NUnit.Framework;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("SimdReg32")]
|
||||
public sealed class CpuTestSimdReg32 : CpuTest32
|
||||
{
|
||||
#if SimdReg32
|
||||
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _1B1H1S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
|
||||
0x0000000000000080ul, 0x00000000000000FFul,
|
||||
0x0000000000007FFFul, 0x0000000000008000ul,
|
||||
0x000000000000FFFFul, 0x000000007FFFFFFFul,
|
||||
0x0000000080000000ul, 0x00000000FFFFFFFFul,
|
||||
0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
|
||||
0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1H1S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
|
||||
0x0000000000008000ul, 0x000000000000FFFFul,
|
||||
0x000000007FFFFFFFul, 0x0000000080000000ul,
|
||||
0x00000000FFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H2S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B4H2S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1S_F_()
|
||||
{
|
||||
yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
|
||||
yield return 0x0000000080800000ul; // -Min Normal
|
||||
yield return 0x00000000807FFFFFul; // -Max Subnormal
|
||||
yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
|
||||
yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
|
||||
yield return 0x0000000000800000ul; // +Min Normal
|
||||
yield return 0x00000000007FFFFFul; // +Max Subnormal
|
||||
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
|
||||
|
||||
if (!NoZeros)
|
||||
{
|
||||
yield return 0x0000000080000000ul; // -Zero
|
||||
yield return 0x0000000000000000ul; // +Zero
|
||||
}
|
||||
|
||||
if (!NoInfs)
|
||||
{
|
||||
yield return 0x00000000FF800000ul; // -Infinity
|
||||
yield return 0x000000007F800000ul; // +Infinity
|
||||
}
|
||||
|
||||
if (!NoNaNs)
|
||||
{
|
||||
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
|
||||
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
|
||||
yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
|
||||
yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
|
||||
}
|
||||
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
|
||||
ulong rnd1 = GenNormalS();
|
||||
ulong rnd2 = GenSubnormalS();
|
||||
|
||||
yield return (grbg << 32) | rnd1;
|
||||
yield return (grbg << 32) | rnd2;
|
||||
}
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _2S_F_()
|
||||
{
|
||||
yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
|
||||
yield return 0x8080000080800000ul; // -Min Normal
|
||||
yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
|
||||
yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
|
||||
yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
|
||||
yield return 0x0080000000800000ul; // +Min Normal
|
||||
yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
|
||||
yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
|
||||
|
||||
if (!NoZeros)
|
||||
{
|
||||
yield return 0x8000000080000000ul; // -Zero
|
||||
yield return 0x0000000000000000ul; // +Zero
|
||||
}
|
||||
|
||||
if (!NoInfs)
|
||||
{
|
||||
yield return 0xFF800000FF800000ul; // -Infinity
|
||||
yield return 0x7F8000007F800000ul; // +Infinity
|
||||
}
|
||||
|
||||
if (!NoNaNs)
|
||||
{
|
||||
yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
|
||||
yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
|
||||
yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
|
||||
yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
|
||||
}
|
||||
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong rnd1 = GenNormalS();
|
||||
ulong rnd2 = GenSubnormalS();
|
||||
|
||||
yield return (rnd1 << 32) | rnd1;
|
||||
yield return (rnd2 << 32) | rnd2;
|
||||
}
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1D_F_()
|
||||
{
|
||||
yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
|
||||
yield return 0x8010000000000000ul; // -Min Normal
|
||||
yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
|
||||
yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
|
||||
yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
|
||||
yield return 0x0010000000000000ul; // +Min Normal
|
||||
yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
|
||||
yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
|
||||
|
||||
if (!NoZeros)
|
||||
{
|
||||
yield return 0x8000000000000000ul; // -Zero
|
||||
yield return 0x0000000000000000ul; // +Zero
|
||||
}
|
||||
|
||||
if (!NoInfs)
|
||||
{
|
||||
yield return 0xFFF0000000000000ul; // -Infinity
|
||||
yield return 0x7FF0000000000000ul; // +Infinity
|
||||
}
|
||||
|
||||
if (!NoNaNs)
|
||||
{
|
||||
yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
|
||||
yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
|
||||
yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
|
||||
yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
|
||||
}
|
||||
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong rnd1 = GenNormalD();
|
||||
ulong rnd2 = GenSubnormalD();
|
||||
|
||||
yield return rnd1;
|
||||
yield return rnd2;
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
private static readonly bool NoZeros = false;
|
||||
private static readonly bool NoInfs = false;
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Explicit]
|
||||
[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
|
||||
public void Vadd_f32([Values(0u)] uint rd,
|
||||
[Values(0u, 1u)] uint rn,
|
||||
[Values(0u, 2u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z0,
|
||||
[ValueSource("_2S_F_")] ulong z1,
|
||||
[ValueSource("_2S_F_")] ulong a0,
|
||||
[ValueSource("_2S_F_")] ulong a1,
|
||||
[ValueSource("_2S_F_")] ulong b0,
|
||||
[ValueSource("_2S_F_")] ulong b1,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2000d00u; // VADD.F32 D0, D0, D0
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rn <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z0, z1);
|
||||
V128 v1 = MakeVectorE0E1(a0, a1);
|
||||
V128 v2 = MakeVectorE0E1(b0, b1);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VCMP.f<size> Vd, Vm")]
|
||||
public void Vcmp([Values(2u, 3u)] uint size,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
[Values] bool e)
|
||||
{
|
||||
uint opcode = 0xeeb40840u;
|
||||
uint rm = 1;
|
||||
uint rd = 2;
|
||||
|
||||
if (size == 3)
|
||||
{
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
|
||||
opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
|
||||
}
|
||||
|
||||
opcode |= ((size & 3) << 8);
|
||||
if (e)
|
||||
{
|
||||
opcode |= 1 << 7;
|
||||
}
|
||||
|
||||
V128 v1 = MakeVectorE0(a);
|
||||
V128 v2 = MakeVectorE0(b);
|
||||
|
||||
bool v = TestContext.CurrentContext.Random.NextBool();
|
||||
bool c = TestContext.CurrentContext.Random.NextBool();
|
||||
bool z = TestContext.CurrentContext.Random.NextBool();
|
||||
bool n = TestContext.CurrentContext.Random.NextBool();
|
||||
|
||||
int fpscr = (int)(TestContext.CurrentContext.Random.NextUInt(0xf) << 28);
|
||||
|
||||
SingleOpcode(opcode, v1: v1, v2: v2, overflow: v, carry: c, zero: z, negative: n, fpscr: fpscr, copyFpFlags: true);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, <Vn>")]
|
||||
public void Vshl([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
[Values] bool q,
|
||||
[Values] bool u)
|
||||
{
|
||||
uint opcode = 0xf2000400u; // VSHL.S8 D0, D0, D0
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rn <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
|
||||
if (u)
|
||||
{
|
||||
opcode |= 1 << 24;
|
||||
}
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
|
||||
opcode |= size << 20;
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Explicit]
|
||||
[Test, Pairwise, Description("VPADD.f32 V0, V0, V0")]
|
||||
public void Vpadd_f32([Values(0u)] uint rd,
|
||||
[Range(0u, 7u)] uint rn,
|
||||
[Range(0u, 7u)] uint rm)
|
||||
{
|
||||
// not currently a slow path test - just a sanity check for pairwise
|
||||
uint opcode = 0xf3000d00u; // VPADD.F32 D0, D0, D0
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
|
||||
var rnd = TestContext.CurrentContext.Random;
|
||||
V128 v0 = new V128(rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue));
|
||||
V128 v1 = new V128(rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue));
|
||||
V128 v2 = new V128(rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue));
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
116
Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
Normal file
116
Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
#define SimdShImm32
|
||||
|
||||
using ARMeilleure.State;
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[Category("SimdShImm32")]
|
||||
public sealed class CpuTestSimdShImm32 : CpuTest32
|
||||
{
|
||||
#if SimdShImm32
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")]
|
||||
public void Vshl_Imm([Values(0u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Random(RndCnt), Values(0u)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2800510u; // VORR.I32 D0, #0 (immediate value changes it into SHL)
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
|
||||
uint imm = 1u << ((int)size + 3);
|
||||
imm |= shiftImm & (imm - 1);
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSHR.<size> {<Vd>}, <Vm>, #<imm>")]
|
||||
public void Vshr_Imm([Values(0u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Random(RndCnt), Values(0u)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR)
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
|
||||
if (u)
|
||||
{
|
||||
opcode |= 1 << 24;
|
||||
}
|
||||
|
||||
uint imm = 1u << ((int)size + 3);
|
||||
imm |= shiftImm & (imm - 1);
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VSHRN.<size> {<Vd>}, <Vm>, #<imm>")]
|
||||
public void Vshrn_Imm([Values(0u, 1u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Random(RndCnt), Values(0u)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b)
|
||||
{
|
||||
uint opcode = 0xf2800810u; // VMOV.I16 D0, #0 (immediate value changes it into SHRN)
|
||||
|
||||
uint imm = 1u << ((int)size + 3);
|
||||
imm |= shiftImm & (imm - 1);
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((imm & 0x3f) << 16);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue