Mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Add SMULL (vector), USHR (scalar), FCCMPE, FNMSUB, fixed a some instructions

Browse source
This commit is contained in:
gdkchan 2018-02-20 14:39:03 -03:00
parent 01b7538560
commit b4a1cfde10
10 changed files with 205 additions and 130 deletions
Download patch file Download diff file Expand all files Collapse all files

46
Ryujinx/Cpu/Instruction/AInstEmitSimdHelper.cs
View file

@ -133,7 +133,7 @@ namespace ChocolArm64.Instruction
public static void EmitScalarOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, bool Signed)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
if (Opers.HasFlag(OperFlags.Rd))
{
@ -147,7 +147,7 @@ namespace ChocolArm64.Instruction
if (Opers.HasFlag(OperFlags.Rm))
{
EmitVectorExtract(Context, Op.Rm, 0, Op.Size, Signed);
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, 0, Op.Size, Signed);
}
Emit();
@ -383,17 +383,17 @@ namespace ChocolArm64.Instruction
}
}
public static void EmitVectorWidenBinaryOpSx(AILEmitterCtx Context, Action Emit)
public static void EmitVectorWidenRmBinaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitVectorWidenBinaryOp(Context, Emit, true);
EmitVectorWidenRmBinaryOp(Context, Emit, true);
}
public static void EmitVectorWidenBinaryOpZx(AILEmitterCtx Context, Action Emit)
public static void EmitVectorWidenRmBinaryOpZx(AILEmitterCtx Context, Action Emit)
{
EmitVectorWidenBinaryOp(Context, Emit, false);
EmitVectorWidenRmBinaryOp(Context, Emit, false);
}
public static void EmitVectorWidenBinaryOp(AILEmitterCtx Context, Action Emit, bool Signed)
public static void EmitVectorWidenRmBinaryOp(AILEmitterCtx Context, Action Emit, bool Signed)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -415,6 +415,38 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Op.Rd);
}
public static void EmitVectorWidenRnRmBinaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitVectorWidenRnRmBinaryOp(Context, Emit, true);
}
public static void EmitVectorWidenRnRmBinaryOpZx(AILEmitterCtx Context, Action Emit)
{
EmitVectorWidenRnRmBinaryOp(Context, Emit, false);
}
public static void EmitVectorWidenRnRmBinaryOp(AILEmitterCtx Context, Action Emit, bool Signed)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Elems = 8 >> Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
EmitVectorExtract(Context, Op.Rm, Part + Index, Op.Size, Signed);
Emit();
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
}
public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
{
EmitVectorZeroAll(Context, Reg);