Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
This commit is contained in:
parent
89ccec197e
commit
c26f3774bd
14 changed files with 873 additions and 288 deletions
7
ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
Normal file
7
ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
Normal file
|
@ -0,0 +1,7 @@
|
|||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
|
||||
{
|
||||
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||
}
|
||||
}
|
Loading…
Add table
Add a link
Reference in a new issue