Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)

* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
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gdkchan 2020-03-10 21:49:27 -03:00 committed by GitHub
parent 89ccec197e
commit c26f3774bd
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14 changed files with 873 additions and 288 deletions

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namespace ARMeilleure.Decoders
{
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
{
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}