Remove old Tester, update Tests (some reworks). (#400)
* Delete Bits.cs * Delete Integer.cs * Delete Instructions.cs * Delete Pseudocode.cs * Add files via upload * Add mnemonic. * Literals all uppercase. * Nit. * Allow FPSR control. * Allow FPSR control. * Allow FPSR control.
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LDj3SNuD
gdkchan
parent
76a3172f17
commit
ca1e37a295
22 changed files with 1354 additions and 15384 deletions
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@ -1,4 +1,4 @@
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//#define CcmpImm
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#define CcmpImm
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using ChocolArm64.State;
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@ -6,25 +6,20 @@ using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
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[Category("CcmpImm")] // Tested: second half of 2018.
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public sealed class CpuTestCcmpImm : CpuTest
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{
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#if CcmpImm
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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private const int RndCntNzcv = 2;
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[Test, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
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[Test, Pairwise, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
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[Random(0u, 15u, 1)] uint nzcv,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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@ -35,29 +30,18 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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CompareAgainstUnicorn();
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}
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[Test, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
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[Test, Pairwise, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
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[Random(0u, 15u, 1)] uint nzcv,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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@ -68,29 +52,18 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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CompareAgainstUnicorn();
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}
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[Test, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
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[Test, Pairwise, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
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[Random(0u, 15u, 1)] uint nzcv,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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@ -101,29 +74,18 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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CompareAgainstUnicorn();
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}
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[Test, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
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[Test, Pairwise, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
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public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
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[Random(0u, 15u, 1)] uint nzcv,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
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[Random(0u, 15u, RndCntNzcv)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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@ -134,20 +96,9 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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CompareAgainstUnicorn();
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}
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#endif
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