Remove old Tester, update Tests (some reworks). (#400)
* Delete Bits.cs * Delete Integer.cs * Delete Instructions.cs * Delete Pseudocode.cs * Add files via upload * Add mnemonic. * Literals all uppercase. * Nit. * Allow FPSR control. * Allow FPSR control. * Allow FPSR control.
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LDj3SNuD
gdkchan
parent
76a3172f17
commit
ca1e37a295
22 changed files with 1354 additions and 15384 deletions
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@ -1,4 +1,4 @@
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//#define Mov
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#define Mov
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using ChocolArm64.State;
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@ -6,23 +6,16 @@ using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Mov"), Ignore("Tested: second half of 2018.")]
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[Category("Mov")] // Tested: second half of 2018.
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public sealed class CpuTestMov : CpuTest
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{
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#if Mov
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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private const int RndCntImm = 2;
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[Test, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movk_64bit([Values(0u, 31u)] uint Rd,
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[Random(12)] ulong _Xd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm,
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[Random(RndCntImm)] ulong _Xd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0
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@ -30,29 +23,16 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rd, new Bits(_Xd));
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Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movk_32bit([Values(0u, 31u)] uint Rd,
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[Random(12)] uint _Wd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm,
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[Random(RndCntImm)] uint _Wd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0
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@ -60,28 +40,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rd, new Bits(_Wd));
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Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movn_64bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0
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@ -89,27 +56,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movn_32bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0
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@ -117,27 +72,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movz_64bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
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@ -145,27 +88,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
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[Test, Pairwise, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movz_32bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0
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@ -173,21 +104,9 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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CompareAgainstUnicorn();
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}
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#endif
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