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391
src/ARMeilleure/Decoders/Decoder.cs
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391
src/ARMeilleure/Decoders/Decoder.cs
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using ARMeilleure.Decoders.Optimizations;
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using ARMeilleure.Instructions;
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using System;
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using System.Collections.Generic;
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using System.Diagnostics;
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namespace ARMeilleure.Decoders
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{
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static class Decoder
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{
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// We define a limit on the number of instructions that a function may have,
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// this prevents functions being potentially too large, which would
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// take too long to compile and use too much memory.
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private const int MaxInstsPerFunction = 2500;
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// For lower code quality translation, we set a lower limit since we're blocking execution.
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private const int MaxInstsPerFunctionLowCq = 500;
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public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode)
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{
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List<Block> blocks = new List<Block>();
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Queue<Block> workQueue = new Queue<Block>();
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Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
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Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction);
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int opsCount = 0;
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int instructionLimit = highCq ? MaxInstsPerFunction : MaxInstsPerFunctionLowCq;
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Block GetBlock(ulong blkAddress)
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{
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if (!visited.TryGetValue(blkAddress, out Block block))
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{
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block = new Block(blkAddress);
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if ((dMode != DecoderMode.MultipleBlocks && visited.Count >= 1) || opsCount > instructionLimit || !memory.IsMapped(blkAddress))
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{
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block.Exit = true;
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block.EndAddress = blkAddress;
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}
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workQueue.Enqueue(block);
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visited.Add(blkAddress, block);
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}
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return block;
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}
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GetBlock(address);
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while (workQueue.TryDequeue(out Block currBlock))
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{
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// Check if the current block is inside another block.
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if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
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{
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Block nBlock = blocks[nBlkIndex];
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if (nBlock.Address == currBlock.Address)
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{
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throw new InvalidOperationException("Found duplicate block address on the list.");
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}
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currBlock.Exit = false;
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nBlock.Split(currBlock);
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blocks.Insert(nBlkIndex + 1, currBlock);
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continue;
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}
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if (!currBlock.Exit)
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{
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// If we have a block after the current one, set the limit address.
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ulong limitAddress = ulong.MaxValue;
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if (nBlkIndex != blocks.Count)
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{
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Block nBlock = blocks[nBlkIndex];
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int nextIndex = nBlkIndex + 1;
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if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
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{
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limitAddress = blocks[nextIndex].Address;
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}
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else if (nBlock.Address > currBlock.Address)
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{
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limitAddress = blocks[nBlkIndex].Address;
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}
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}
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if (dMode == DecoderMode.SingleInstruction)
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{
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// Only read at most one instruction
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limitAddress = currBlock.Address + 1;
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}
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FillBlock(memory, mode, currBlock, limitAddress);
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opsCount += currBlock.OpCodes.Count;
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if (currBlock.OpCodes.Count != 0)
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{
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// Set child blocks. "Branch" is the block the branch instruction
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// points to (when taken), "Next" is the block at the next address,
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// executed when the branch is not taken. For Unconditional Branches
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// (except BL/BLR that are sub calls) or end of executable, Next is null.
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OpCode lastOp = currBlock.GetLastOp();
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bool isCall = IsCall(lastOp);
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if (lastOp is IOpCodeBImm op && !isCall)
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{
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currBlock.Branch = GetBlock((ulong)op.Immediate);
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}
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if (isCall || !(IsUnconditionalBranch(lastOp) || IsTrap(lastOp)))
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{
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currBlock.Next = GetBlock(currBlock.EndAddress);
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}
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}
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}
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// Insert the new block on the list (sorted by address).
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if (blocks.Count != 0)
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{
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Block nBlock = blocks[nBlkIndex];
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blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
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}
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else
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{
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blocks.Add(currBlock);
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}
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}
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if (blocks.Count == 1 && blocks[0].OpCodes.Count == 0)
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{
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Debug.Assert(blocks[0].Exit);
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Debug.Assert(blocks[0].Address == blocks[0].EndAddress);
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throw new InvalidOperationException($"Decoded a single empty exit block. Entry point = 0x{address:X}.");
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}
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if (dMode == DecoderMode.MultipleBlocks)
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{
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return TailCallRemover.RunPass(address, blocks);
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}
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else
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{
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return blocks.ToArray();
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}
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}
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public static bool BinarySearch(List<Block> blocks, ulong address, out int index)
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{
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index = 0;
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int left = 0;
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int right = blocks.Count - 1;
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while (left <= right)
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{
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int size = right - left;
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int middle = left + (size >> 1);
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Block block = blocks[middle];
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index = middle;
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if (address >= block.Address && address < block.EndAddress)
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{
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return true;
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}
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if (address < block.Address)
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{
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right = middle - 1;
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}
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else
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{
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left = middle + 1;
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}
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}
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return false;
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}
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private static void FillBlock(
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IMemoryManager memory,
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ExecutionMode mode,
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Block block,
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ulong limitAddress)
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{
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ulong address = block.Address;
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int itBlockSize = 0;
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OpCode opCode;
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do
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{
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if (address >= limitAddress && itBlockSize == 0)
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{
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break;
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}
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opCode = DecodeOpCode(memory, address, mode);
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block.OpCodes.Add(opCode);
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address += (ulong)opCode.OpCodeSizeInBytes;
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if (opCode is OpCodeT16IfThen it)
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{
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itBlockSize = it.IfThenBlockSize;
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}
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else if (itBlockSize > 0)
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{
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itBlockSize--;
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}
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}
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while (!(IsBranch(opCode) || IsException(opCode)));
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block.EndAddress = address;
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}
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private static bool IsBranch(OpCode opCode)
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{
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return opCode is OpCodeBImm ||
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opCode is OpCodeBReg || IsAarch32Branch(opCode);
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}
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private static bool IsUnconditionalBranch(OpCode opCode)
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{
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return opCode is OpCodeBImmAl ||
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opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
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}
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private static bool IsAarch32UnconditionalBranch(OpCode opCode)
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{
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if (!(opCode is OpCode32 op))
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{
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return false;
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}
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// Compare and branch instructions are always conditional.
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if (opCode.Instruction.Name == InstName.Cbz ||
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opCode.Instruction.Name == InstName.Cbnz)
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{
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return false;
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}
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// Note: On ARM32, most instructions have conditional execution,
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// so there's no "Always" (unconditional) branch like on ARM64.
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// We need to check if the condition is "Always" instead.
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return IsAarch32Branch(op) && op.Cond >= Condition.Al;
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}
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private static bool IsAarch32Branch(OpCode opCode)
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{
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// Note: On ARM32, most ALU operations can write to R15 (PC),
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// so we must consider such operations as a branch in potential aswell.
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if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
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{
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if (opCode is OpCodeT32)
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{
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return opCode.Instruction.Name != InstName.Tst && opCode.Instruction.Name != InstName.Teq &&
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opCode.Instruction.Name != InstName.Cmp && opCode.Instruction.Name != InstName.Cmn;
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}
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return true;
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}
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// Same thing for memory operations. We have the cases where PC is a target
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// register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
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// a write back to PC (wback == true && Rn == 15), however the later may
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// be "undefined" depending on the CPU, so compilers should not produce that.
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if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
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{
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int rt, rn;
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bool wBack, isLoad;
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if (opCode is IOpCode32Mem opMem)
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{
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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isLoad = opMem.IsLoad;
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// For the dual load, we also need to take into account the
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// case were Rt2 == 15 (PC).
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if (rt == 14 && opMem.Instruction.Name == InstName.Ldrd)
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{
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rt = RegisterAlias.Aarch32Pc;
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}
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}
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else if (opCode is IOpCode32MemMult opMemMult)
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{
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const int pcMask = 1 << RegisterAlias.Aarch32Pc;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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}
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else
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{
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throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
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}
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if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
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(rn == RegisterAlias.Aarch32Pc && wBack))
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{
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return true;
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}
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}
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// Explicit branch instructions.
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return opCode is IOpCode32BImm ||
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opCode is IOpCode32BReg;
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}
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private static bool IsCall(OpCode opCode)
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{
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return opCode.Instruction.Name == InstName.Bl ||
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opCode.Instruction.Name == InstName.Blr ||
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opCode.Instruction.Name == InstName.Blx;
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}
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private static bool IsException(OpCode opCode)
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{
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return IsTrap(opCode) || opCode.Instruction.Name == InstName.Svc;
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}
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private static bool IsTrap(OpCode opCode)
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{
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return opCode.Instruction.Name == InstName.Brk ||
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opCode.Instruction.Name == InstName.Trap ||
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opCode.Instruction.Name == InstName.Und;
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}
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public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode)
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{
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int opCode = memory.Read<int>(address);
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InstDescriptor inst;
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OpCodeTable.MakeOp makeOp;
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if (mode == ExecutionMode.Aarch64)
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{
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(inst, makeOp) = OpCodeTable.GetInstA64(opCode);
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}
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else
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{
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if (mode == ExecutionMode.Aarch32Arm)
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{
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(inst, makeOp) = OpCodeTable.GetInstA32(opCode);
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}
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else /* if (mode == ExecutionMode.Aarch32Thumb) */
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{
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(inst, makeOp) = OpCodeTable.GetInstT32(opCode);
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}
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}
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if (makeOp != null)
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{
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return makeOp(inst, address, opCode);
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}
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else
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{
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if (mode == ExecutionMode.Aarch32Thumb)
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{
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return new OpCodeT16(inst, address, opCode);
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}
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else
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{
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return new OpCode(inst, address, opCode);
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}
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}
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}
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}
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}
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