Move solution and projects to src
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TSR Berry
Mary
parent
cd124bda58
commit
cee7121058
3466 changed files with 55 additions and 55 deletions
541
src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
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541
src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
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@ -0,0 +1,541 @@
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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private enum MemoryRegion
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{
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Local,
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Shared
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}
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public static void Atom(EmitterContext context)
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{
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InstAtom op = context.GetOp<InstAtom>();
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int sOffset = (op.Imm20 << 12) >> 12;
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, new Register(op.SrcA, RegisterType.Gpr), op.E, sOffset);
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Operand value = GetSrcReg(context, op.SrcB);
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Operand res = EmitAtomicOp(context, StorageKind.GlobalMemory, op.Op, op.Size, addrLow, addrHigh, value);
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context.Copy(GetDest(op.Dest), res);
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}
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public static void Atoms(EmitterContext context)
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{
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InstAtoms op = context.GetOp<InstAtoms>();
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Operand offset = context.ShiftRightU32(GetSrcReg(context, op.SrcA), Const(2));
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int sOffset = (op.Imm22 << 10) >> 10;
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offset = context.IAdd(offset, Const(sOffset));
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Operand value = GetSrcReg(context, op.SrcB);
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AtomSize size = op.AtomsSize switch
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{
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AtomsSize.S32 => AtomSize.S32,
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AtomsSize.U64 => AtomSize.U64,
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AtomsSize.S64 => AtomSize.S64,
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_ => AtomSize.U32
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};
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Operand res = EmitAtomicOp(context, StorageKind.SharedMemory, op.AtomOp, size, offset, Const(0), value);
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context.Copy(GetDest(op.Dest), res);
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}
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public static void Ldc(EmitterContext context)
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{
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InstLdc op = context.GetOp<InstLdc>();
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if (op.LsSize > LsSize2.B64)
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{
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context.Config.GpuAccessor.Log($"Invalid LDC size: {op.LsSize}.");
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return;
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}
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bool isSmallInt = op.LsSize < LsSize2.B32;
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int count = op.LsSize == LsSize2.B64 ? 2 : 1;
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Operand slot = Const(op.CbufSlot);
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Operand srcA = GetSrcReg(context, op.SrcA);
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if (op.AddressMode == AddressMode.Is || op.AddressMode == AddressMode.Isl)
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{
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slot = context.IAdd(slot, context.BitfieldExtractU32(srcA, Const(16), Const(16)));
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srcA = context.BitwiseAnd(srcA, Const(0xffff));
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}
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Operand addr = context.IAdd(srcA, Const(Imm16ToSInt(op.CbufOffset)));
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Operand wordOffset = context.ShiftRightU32(addr, Const(2));
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Operand bitOffset = GetBitOffset(context, addr);
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for (int index = 0; index < count; index++)
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{
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Register dest = new Register(op.Dest + index, RegisterType.Gpr);
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if (dest.IsRZ)
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{
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break;
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}
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Operand offset = context.IAdd(wordOffset, Const(index));
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Operand value = context.LoadConstant(slot, offset);
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, (LsSize)op.LsSize, bitOffset, value);
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}
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context.Copy(Register(dest), value);
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}
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}
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public static void Ldg(EmitterContext context)
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{
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InstLdg op = context.GetOp<InstLdg>();
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EmitLdg(context, op.LsSize, op.SrcA, op.Dest, Imm24ToSInt(op.Imm24), op.E);
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}
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public static void Ldl(EmitterContext context)
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{
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InstLdl op = context.GetOp<InstLdl>();
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EmitLoad(context, MemoryRegion.Local, op.LsSize, GetSrcReg(context, op.SrcA), op.Dest, Imm24ToSInt(op.Imm24));
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}
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public static void Lds(EmitterContext context)
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{
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InstLds op = context.GetOp<InstLds>();
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EmitLoad(context, MemoryRegion.Shared, op.LsSize, GetSrcReg(context, op.SrcA), op.Dest, Imm24ToSInt(op.Imm24));
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}
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public static void Red(EmitterContext context)
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{
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InstRed op = context.GetOp<InstRed>();
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, new Register(op.SrcA, RegisterType.Gpr), op.E, op.Imm20);
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EmitAtomicOp(context, StorageKind.GlobalMemory, (AtomOp)op.RedOp, op.RedSize, addrLow, addrHigh, GetDest(op.SrcB));
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}
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public static void Stg(EmitterContext context)
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{
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InstStg op = context.GetOp<InstStg>();
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EmitStg(context, op.LsSize, op.SrcA, op.Dest, Imm24ToSInt(op.Imm24), op.E);
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}
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public static void Stl(EmitterContext context)
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{
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InstStl op = context.GetOp<InstStl>();
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EmitStore(context, MemoryRegion.Local, op.LsSize, GetSrcReg(context, op.SrcA), op.Dest, Imm24ToSInt(op.Imm24));
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}
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public static void Sts(EmitterContext context)
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{
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InstSts op = context.GetOp<InstSts>();
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EmitStore(context, MemoryRegion.Shared, op.LsSize, GetSrcReg(context, op.SrcA), op.Dest, Imm24ToSInt(op.Imm24));
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}
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private static Operand EmitAtomicOp(
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EmitterContext context,
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StorageKind storageKind,
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AtomOp op,
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AtomSize type,
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Operand addrLow,
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Operand addrHigh,
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Operand value)
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{
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Operand res = Const(0);
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switch (op)
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{
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case AtomOp.Add:
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if (type == AtomSize.S32 || type == AtomSize.U32)
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{
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res = context.AtomicAdd(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomOp.And:
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if (type == AtomSize.S32 || type == AtomSize.U32)
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{
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res = context.AtomicAnd(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomOp.Xor:
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if (type == AtomSize.S32 || type == AtomSize.U32)
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{
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res = context.AtomicXor(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomOp.Or:
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if (type == AtomSize.S32 || type == AtomSize.U32)
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{
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res = context.AtomicOr(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomOp.Max:
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if (type == AtomSize.S32)
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{
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res = context.AtomicMaxS32(storageKind, addrLow, addrHigh, value);
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}
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else if (type == AtomSize.U32)
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{
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res = context.AtomicMaxU32(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomOp.Min:
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if (type == AtomSize.S32)
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{
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res = context.AtomicMinS32(storageKind, addrLow, addrHigh, value);
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}
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else if (type == AtomSize.U32)
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{
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res = context.AtomicMinU32(storageKind, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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}
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return res;
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}
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private static void EmitLoad(
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EmitterContext context,
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MemoryRegion region,
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LsSize2 size,
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Operand srcA,
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int rd,
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int offset)
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{
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if (size > LsSize2.B128)
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{
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context.Config.GpuAccessor.Log($"Invalid load size: {size}.");
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return;
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}
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bool isSmallInt = size < LsSize2.B32;
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int count = 1;
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switch (size)
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{
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case LsSize2.B64: count = 2; break;
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case LsSize2.B128: count = 4; break;
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}
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Operand baseOffset = context.IAdd(srcA, Const(offset));
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Operand wordOffset = context.ShiftRightU32(baseOffset, Const(2)); // Word offset = byte offset / 4 (one word = 4 bytes).
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Operand bitOffset = GetBitOffset(context, baseOffset);
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for (int index = 0; index < count; index++)
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{
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Register dest = new Register(rd + index, RegisterType.Gpr);
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if (dest.IsRZ)
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{
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break;
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}
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Operand elemOffset = context.IAdd(wordOffset, Const(index));
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Operand value = null;
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switch (region)
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{
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case MemoryRegion.Local: value = context.LoadLocal(elemOffset); break;
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case MemoryRegion.Shared: value = context.LoadShared(elemOffset); break;
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}
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, (LsSize)size, bitOffset, value);
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}
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context.Copy(Register(dest), value);
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}
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}
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private static void EmitLdg(
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EmitterContext context,
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LsSize size,
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int ra,
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int rd,
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int offset,
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bool extended)
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{
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bool isSmallInt = size < LsSize.B32;
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int count = GetVectorCount(size);
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, new Register(ra, RegisterType.Gpr), extended, offset);
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Operand bitOffset = GetBitOffset(context, addrLow);
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for (int index = 0; index < count; index++)
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{
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Register dest = new Register(rd + index, RegisterType.Gpr);
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if (dest.IsRZ)
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{
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break;
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}
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Operand value = context.LoadGlobal(context.IAdd(addrLow, Const(index * 4)), addrHigh);
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, size, bitOffset, value);
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}
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context.Copy(Register(dest), value);
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}
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}
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private static void EmitStore(
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EmitterContext context,
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MemoryRegion region,
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LsSize2 size,
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Operand srcA,
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int rd,
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int offset)
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{
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if (size > LsSize2.B128)
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{
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context.Config.GpuAccessor.Log($"Invalid store size: {size}.");
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return;
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}
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bool isSmallInt = size < LsSize2.B32;
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int count = 1;
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switch (size)
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{
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case LsSize2.B64: count = 2; break;
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case LsSize2.B128: count = 4; break;
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}
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Operand baseOffset = context.IAdd(srcA, Const(offset));
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Operand wordOffset = context.ShiftRightU32(baseOffset, Const(2));
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Operand bitOffset = GetBitOffset(context, baseOffset);
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for (int index = 0; index < count; index++)
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{
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bool isRz = rd + index >= RegisterConsts.RegisterZeroIndex;
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Operand value = Register(isRz ? rd : rd + index, RegisterType.Gpr);
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Operand elemOffset = context.IAdd(wordOffset, Const(index));
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if (isSmallInt && region == MemoryRegion.Local)
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{
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Operand word = context.LoadLocal(elemOffset);
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value = InsertSmallInt(context, (LsSize)size, bitOffset, word, value);
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}
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if (region == MemoryRegion.Local)
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{
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context.StoreLocal(elemOffset, value);
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}
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else if (region == MemoryRegion.Shared)
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{
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switch (size)
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{
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case LsSize2.U8:
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case LsSize2.S8:
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context.StoreShared8(baseOffset, value);
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break;
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case LsSize2.U16:
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case LsSize2.S16:
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context.StoreShared16(baseOffset, value);
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break;
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default:
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context.StoreShared(elemOffset, value);
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break;
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}
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}
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}
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}
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private static void EmitStg(
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EmitterContext context,
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LsSize2 size,
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int ra,
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int rd,
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int offset,
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bool extended)
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{
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if (size > LsSize2.B128)
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{
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context.Config.GpuAccessor.Log($"Invalid store size: {size}.");
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return;
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}
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int count = GetVectorCount((LsSize)size);
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, new Register(ra, RegisterType.Gpr), extended, offset);
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Operand bitOffset = GetBitOffset(context, addrLow);
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for (int index = 0; index < count; index++)
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{
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bool isRz = rd + index >= RegisterConsts.RegisterZeroIndex;
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Operand value = Register(isRz ? rd : rd + index, RegisterType.Gpr);
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Operand addrLowOffset = context.IAdd(addrLow, Const(index * 4));
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if (size == LsSize2.U8 || size == LsSize2.S8)
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{
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context.StoreGlobal8(addrLowOffset, addrHigh, value);
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}
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else if (size == LsSize2.U16 || size == LsSize2.S16)
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{
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context.StoreGlobal16(addrLowOffset, addrHigh, value);
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}
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else
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{
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context.StoreGlobal(addrLowOffset, addrHigh, value);
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}
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}
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}
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private static int GetVectorCount(LsSize size)
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{
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switch (size)
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{
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case LsSize.B64:
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return 2;
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case LsSize.B128:
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case LsSize.UB128:
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return 4;
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}
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return 1;
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}
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private static (Operand, Operand) Get40BitsAddress(
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EmitterContext context,
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Register ra,
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bool extended,
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int offset)
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{
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Operand addrLow = Register(ra);
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Operand addrHigh;
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if (extended && !ra.IsRZ)
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{
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addrHigh = Register(ra.Index + 1, RegisterType.Gpr);
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}
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else
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{
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addrHigh = Const(0);
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}
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Operand offs = Const(offset);
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addrLow = context.IAdd(addrLow, offs);
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if (extended)
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{
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Operand carry = context.ICompareLessUnsigned(addrLow, offs);
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addrHigh = context.IAdd(addrHigh, context.ConditionalSelect(carry, Const(1), Const(0)));
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}
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return (addrLow, addrHigh);
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}
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private static Operand GetBitOffset(EmitterContext context, Operand baseOffset)
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{
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// Note: bit offset = (baseOffset & 0b11) * 8.
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// Addresses should be always aligned to the integer type,
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// so we don't need to take unaligned addresses into account.
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return context.ShiftLeft(context.BitwiseAnd(baseOffset, Const(3)), Const(3));
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}
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private static Operand ExtractSmallInt(
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EmitterContext context,
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LsSize size,
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Operand bitOffset,
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Operand value)
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{
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value = context.ShiftRightU32(value, bitOffset);
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switch (size)
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{
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case LsSize.U8: value = ZeroExtendTo32(context, value, 8); break;
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case LsSize.U16: value = ZeroExtendTo32(context, value, 16); break;
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case LsSize.S8: value = SignExtendTo32(context, value, 8); break;
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case LsSize.S16: value = SignExtendTo32(context, value, 16); break;
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}
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return value;
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}
|
||||
|
||||
private static Operand InsertSmallInt(
|
||||
EmitterContext context,
|
||||
LsSize size,
|
||||
Operand bitOffset,
|
||||
Operand word,
|
||||
Operand value)
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case LsSize.U8:
|
||||
case LsSize.S8:
|
||||
value = context.BitwiseAnd(value, Const(0xff));
|
||||
value = context.BitfieldInsert(word, value, bitOffset, Const(8));
|
||||
break;
|
||||
|
||||
case LsSize.U16:
|
||||
case LsSize.S16:
|
||||
value = context.BitwiseAnd(value, Const(0xffff));
|
||||
value = context.BitfieldInsert(word, value, bitOffset, Const(16));
|
||||
break;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue