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Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)

Browse source 
* Update CpuTestAlu.cs

* Update CpuTestSimd.cs

* Update CpuTestMov.cs
This commit is contained in:
LDj3SNuD 2019-06-12 14:03:31 +02:00 • committed by gdkchan
parent 3541a9053f
commit d87c5375f1
3 changed files with 292 additions and 40 deletions
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5
Ryujinx.Tests/Cpu/CpuTestMov.cs
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@ -8,11 +8,12 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestMov : CpuTest
{
#if Mov
private const int RndCnt = 2;
private const int RndCntImm = 2;
[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
public void Movk_64bit([Values(0u, 31u)] uint rd,
[Random(RndCntImm)] ulong xd,
[Random(RndCnt)] ulong xd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
@ -29,7 +30,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
public void Movk_32bit([Values(0u, 31u)] uint rd,
[Random(RndCntImm)] uint wd,
[Random(RndCnt)] uint wd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{