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Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)

Browse source 
* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
This commit is contained in:
LDj3SNuD 2018-10-23 16:12:45 +02:00 • committed by gdkchan
parent 7920dc1d2f
commit e674b37710
18 changed files with 863 additions and 200 deletions
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17
ChocolArm64/Instruction/AInstEmitSimdCmp.cs
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@ -284,11 +284,11 @@ namespace ChocolArm64.Instruction
{
if (Op.Size == 0)
{
Context.EmitLdc_R4(0);
Context.EmitLdc_R4(0f);
}
else /* if (SizeF == 1) */
else /* if (Op.Size == 1) */
{
Context.EmitLdc_R8(0);
Context.EmitLdc_R8(0d);
}
}
else
@ -378,7 +378,7 @@ namespace ChocolArm64.Instruction
}
else
{
Context.EmitLdc_I8(0);
Context.EmitLdc_I8(0L);
}
AILLabel LblTrue = new AILLabel();
@ -422,7 +422,7 @@ namespace ChocolArm64.Instruction
Context.Emit(OpCodes.And);
Context.EmitLdc_I8(0);
Context.EmitLdc_I8(0L);
Context.Emit(OpCodes.Bne_Un_S, LblTrue);
@ -455,8 +455,9 @@ namespace ChocolArm64.Instruction
int SizeF = Op.Size & 1;
int Bytes = Op.GetBitsCount() >> 3;
int Elems = Bytes >> SizeF + 2;
for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
for (int Index = 0; Index < Elems; Index++)
{
EmitFcmp(Context, ILOp, Index, Scalar: false);
}
@ -483,11 +484,11 @@ namespace ChocolArm64.Instruction
}
else if (SizeF == 0)
{
Context.EmitLdc_R4(0);
Context.EmitLdc_R4(0f);
}
else /* if (SizeF == 1) */
{
Context.EmitLdc_R8(0);
Context.EmitLdc_R8(0d);
}
AILLabel LblTrue = new AILLabel();