Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)
* Update CpuTest.cs * Update CpuTestSimd.cs * Superseded. * Update AInstEmitSimdCvt.cs * Update ASoftFloat.cs * Nit. * Update PackageReferences. * Update AInstEmitSimdArithmetic.cs * Update AVectorHelper.cs * Update ASoftFloat.cs * Update ASoftFallback.cs * Update AThreadState.cs * Create FPType.cs * Create FPExc.cs * Create FPCR.cs * Create FPSR.cs * Update ARoundMode.cs * Update APState.cs * Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover. * Nits.
This commit is contained in:
parent
7920dc1d2f
commit
e674b37710
18 changed files with 863 additions and 200 deletions
|
@ -105,9 +105,9 @@ namespace ChocolArm64.Instruction
|
|||
Value < ulong.MinValue ? ulong.MinValue : (ulong)Value;
|
||||
}
|
||||
|
||||
public static double Round(double Value, int Fpcr)
|
||||
public static double Round(double Value, AThreadState State)
|
||||
{
|
||||
switch ((ARoundMode)((Fpcr >> 22) & 3))
|
||||
switch (State.FPRoundingMode())
|
||||
{
|
||||
case ARoundMode.ToNearest: return Math.Round (Value);
|
||||
case ARoundMode.TowardsPlusInfinity: return Math.Ceiling (Value);
|
||||
|
@ -118,9 +118,9 @@ namespace ChocolArm64.Instruction
|
|||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
public static float RoundF(float Value, int Fpcr)
|
||||
public static float RoundF(float Value, AThreadState State)
|
||||
{
|
||||
switch ((ARoundMode)((Fpcr >> 22) & 3))
|
||||
switch (State.FPRoundingMode())
|
||||
{
|
||||
case ARoundMode.ToNearest: return MathF.Round (Value);
|
||||
case ARoundMode.TowardsPlusInfinity: return MathF.Ceiling (Value);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue