Add 151 complete tests for 71 base instructions of types: Alu; AluImm; AluRs; AluRx; Bfm; CcmpImm; CcmpReg; Csel; Mov; Mul. (#80)
* Add files via upload * Update Ryujinx.Tests.csproj
This commit is contained in:
LDj3SNuD
gdkchan
parent
8b75080639
commit
e9a96e3522
17 changed files with 8833 additions and 263 deletions
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@ -1,162 +1,331 @@
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//#define Alu
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestAlu : CpuTest
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using Tester;
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using Tester.Types;
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[Category("Alu"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestAlu : CpuTest
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{
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[TestCase(0x9A020020u, 2u, 3u, true, 6u)]
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[TestCase(0x9A020020u, 2u, 3u, false, 5u)]
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[TestCase(0x1A020020u, 2u, 3u, true, 6u)]
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[TestCase(0x1A020020u, 2u, 3u, false, 5u)]
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[TestCase(0x1A020020u, 0xFFFFFFFFu, 0x2u, false, 0x1u)]
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public void Adc(uint Opcode, uint A, uint B, bool CarryState, uint Result)
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#if Alu
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[SetUp]
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public void SetupTester()
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{
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// ADC (X0/W0), (X1/W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.AreEqual(Result, ThreadState.X0);
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AArch64.TakeReset(false);
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}
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[TestCase(0x3A020020u, 2u, 3u, false, false, false, false, 5u)]
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[TestCase(0x3A020020u, 2u, 3u, true, false, false, false, 6u)]
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[TestCase(0xBA020020u, 2u, 3u, false, false, false, false, 5u)]
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[TestCase(0xBA020020u, 2u, 3u, true, false, false, false, 6u)]
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[TestCase(0x3A020020u, 0xFFFFFFFEu, 0x1u, true, false, true, true, 0x0u)]
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[TestCase(0x3A020020u, 0xFFFFFFFFu, 0xFFFFFFFFu, true, true, false, true, 0xFFFFFFFFu)]
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public void Adcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result)
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[Test, Description("CLS <Xd>, <Xn>")]
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public void Cls_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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//ADCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.Multiple(() =>
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uint Opcode = 0xDAC01400; // CLS X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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}
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[Test]
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public void Add()
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{
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// ADD X0, X1, X2
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AThreadState ThreadState = SingleOpcode(0x8B020020, X1: 1, X2: 2);
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Assert.AreEqual(3, ThreadState.X0);
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}
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Bits Op = new Bits(Opcode);
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[TestCase(2u, false, false)]
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[TestCase(5u, false, false)]
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[TestCase(7u, false, false)]
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[TestCase(0xFFFFFFFFu, false, true )]
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[TestCase(0xFFFFFFFBu, true, true )]
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public void Adds(uint A, bool Zero, bool Carry)
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{
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//ADDS WZR, WSP, #5
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AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A);
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Assert.Multiple(() =>
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.IsFalse(ThreadState.Negative);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(A, ThreadState.X31);
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});
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
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[TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)]
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[TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)]
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public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero)
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[Test, Description("CLS <Wd>, <Wn>")]
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public void Cls_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B);
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Assert.Multiple(() =>
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uint Opcode = 0x5AC01400; // CLS W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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});
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}
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Bits Op = new Bits(Opcode);
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[TestCase(0x0000FF44u, 0x00000004u, 0x00000FF4u)]
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[TestCase(0x00000000u, 0x00000004u, 0x00000000u)]
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[TestCase(0x0000FF44u, 0x00000008u, 0x000000FFu)]
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[TestCase(0xFFFFFFFFu, 0x00000004u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000008u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000020u, 0xFFFFFFFFu)]
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[TestCase(0x0FFFFFFFu, 0x0000001Cu, 0x00000000u)]
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[TestCase(0x80000000u, 0x0000001Fu, 0xFFFFFFFFu)]
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[TestCase(0xCAFE0000u, 0x00000020u, 0xCAFE0000u)]
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public void Asrv32(uint A, uint ShiftValue, uint Result)
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{
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// ASRV W0, W1, W2
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AThreadState ThreadState = SingleOpcode(0x1AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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[TestCase(0x000000000000FF44ul, 0x00000004u, 0x0000000000000FF4ul)]
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[TestCase(0x0000000000000000ul, 0x00000004u, 0x0000000000000000ul)]
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[TestCase(0x000000000000FF44ul, 0x00000008u, 0x00000000000000FFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000004u, 0x000000000FFFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000008u, 0x0000000000FFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000020u, 0x0000000000000000ul)]
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[TestCase(0x000000000FFFFFFFul, 0x0000001Cu, 0x0000000000000000ul)]
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[TestCase(0x000CC4488FFFFFFFul, 0x0000001Cu, 0x0000000000CC4488ul)]
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[TestCase(0xFFFFFFFFFFFFFFFFul, 0x0000001Cu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0x8000000000000000ul, 0x0000003Fu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0xCAFE000000000000ul, 0x00000040u, 0xCAFE000000000000ul)]
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public void Asrv64(ulong A, uint ShiftValue, ulong Result)
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{
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// ASRV X0, X1, X2
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AThreadState ThreadState = SingleOpcode(0x9AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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[TestCase(0x01010101u, 0x3200C3E2u)]
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[TestCase(0x00F000F0u, 0x320C8FE2u)]
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[TestCase(0x00000001u, 0x320003E2u)]
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public void OrrBitmasks(uint Bitmask, uint Opcode)
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{
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// ORR W2, WZR, #Bitmask
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Assert.AreEqual(Bitmask, SingleOpcode(Opcode).X2);
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}
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[Test]
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public void RevX0X0()
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{
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// REV X0, X0
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AThreadState ThreadState = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100);
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Assert.AreEqual(0x0011FFEEDDCCBBAA, ThreadState.X0);
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}
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[Test]
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public void RevW1W1()
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{
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// REV W1, W1
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AThreadState ThreadState = SingleOpcode(0x5AC00821, X1: 0x12345678);
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Assert.AreEqual(0x78563412, ThreadState.X1);
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}
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[TestCase(0x7A020020u, 4u, 2u, false, false, false, true, 1u)]
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[TestCase(0x7A020020u, 4u, 2u, true, false, false, true, 2u)]
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[TestCase(0xFA020020u, 4u, 2u, false, false, false, true, 1u)]
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[TestCase(0xFA020020u, 4u, 2u, true, false, false, true, 2u)]
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[TestCase(0x7A020020u, 4u, 4u, false, true, false, false, 0xFFFFFFFFu)]
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[TestCase(0x7A020020u, 4u, 4u, true, false, true, true, 0x0u)]
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public void Sbcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result)
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{
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//SBCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.Multiple(() =>
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("CLZ <Xd>, <Xn>")]
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public void Clz_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC01000; // CLZ X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("CLZ <Wd>, <Wn>")]
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public void Clz_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC01000; // CLZ W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("RBIT <Xd>, <Xn>")]
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public void Rbit_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00000; // RBIT X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("RBIT <Wd>, <Wn>")]
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public void Rbit_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC00000; // RBIT W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("REV16 <Xd>, <Xn>")]
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public void Rev16_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00400; // REV16 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("REV16 <Wd>, <Wn>")]
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public void Rev16_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC00400; // REV16 W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("REV32 <Xd>, <Xn>")]
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public void Rev32_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
|
||||
{
|
||||
uint Opcode = 0xDAC00800; // REV32 X0, X0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
|
||||
if (Rd != 31)
|
||||
{
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AArch64.X((int)Rn, new Bits(Xn));
|
||||
Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
|
||||
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
|
||||
|
||||
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
|
||||
}
|
||||
}
|
||||
|
||||
[Test, Description("REV <Wd>, <Wn>")]
|
||||
public void Rev32_32bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
|
||||
{
|
||||
uint Opcode = 0x5AC00800; // REV W0, W0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
|
||||
|
||||
if (Rd != 31)
|
||||
{
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AArch64.X((int)Rn, new Bits(Wn));
|
||||
Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
|
||||
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
|
||||
|
||||
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
|
||||
}
|
||||
}
|
||||
|
||||
[Test, Description("REV64 <Xd>, <Xn>")]
|
||||
public void Rev64_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
|
||||
{
|
||||
uint Opcode = 0xDAC00C00; // REV64 X0, X0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
|
||||
if (Rd != 31)
|
||||
{
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AArch64.X((int)Rn, new Bits(Xn));
|
||||
Base.Rev64(Op[9, 5], Op[4, 0]);
|
||||
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
|
||||
|
||||
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
|
||||
}
|
||||
else
|
||||
{
|
||||
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue