Replace unicorn bindings with Nuget package (#4378)
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
This commit is contained in:
TSRBerry
GitHub
parent
b3f0978869
commit
ec8d4f3af5
64 changed files with 2276 additions and 3576 deletions
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@ -8,17 +8,13 @@ namespace Ryujinx.Tests.Cpu
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public sealed class CpuTestAluImm : CpuTest
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{
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#if AluImm
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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private const int RndCntImms = 2;
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private const int RndCntImmr = 2;
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[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
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public void Add_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
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@ -41,8 +37,8 @@ namespace Ryujinx.Tests.Cpu
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public void Add_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
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@ -65,8 +61,8 @@ namespace Ryujinx.Tests.Cpu
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public void Adds_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
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@ -89,8 +85,8 @@ namespace Ryujinx.Tests.Cpu
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public void Adds_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
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@ -113,9 +109,9 @@ namespace Ryujinx.Tests.Cpu
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public void And_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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{
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uint opcode = 0x92400000; // AND X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -132,9 +128,9 @@ namespace Ryujinx.Tests.Cpu
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public void And_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0x92000000; // AND X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -151,9 +147,9 @@ namespace Ryujinx.Tests.Cpu
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public void And_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0x12000000; // AND W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -170,9 +166,9 @@ namespace Ryujinx.Tests.Cpu
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public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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{
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uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -189,9 +185,9 @@ namespace Ryujinx.Tests.Cpu
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public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -208,9 +204,9 @@ namespace Ryujinx.Tests.Cpu
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public void Ands_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0x72000000; // ANDS W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -227,9 +223,9 @@ namespace Ryujinx.Tests.Cpu
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public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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{
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uint opcode = 0xD2400000; // EOR X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -246,9 +242,9 @@ namespace Ryujinx.Tests.Cpu
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public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -265,9 +261,9 @@ namespace Ryujinx.Tests.Cpu
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public void Eor_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0x52000000; // EOR W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -284,9 +280,9 @@ namespace Ryujinx.Tests.Cpu
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public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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{
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uint opcode = 0xB2400000; // ORR X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -303,9 +299,9 @@ namespace Ryujinx.Tests.Cpu
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public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -322,9 +318,9 @@ namespace Ryujinx.Tests.Cpu
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public void Orr_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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{
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uint opcode = 0x32000000; // ORR W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -341,8 +337,8 @@ namespace Ryujinx.Tests.Cpu
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public void Sub_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
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@ -365,8 +361,8 @@ namespace Ryujinx.Tests.Cpu
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public void Sub_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
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@ -389,8 +385,8 @@ namespace Ryujinx.Tests.Cpu
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public void Subs_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
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@ -413,8 +409,8 @@ namespace Ryujinx.Tests.Cpu
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public void Subs_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
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@ -434,4 +430,4 @@ namespace Ryujinx.Tests.Cpu
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}
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#endif
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}
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}
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}
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