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Replace unicorn bindings with Nuget package (#4378)

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* Replace unicorn bindings with Nuget package

* Use nameof for ValueSource args

* Remove redundant code from test projects

* Fix wrong values for EmuStart()

Add notes to address this later again

* Improve formatting

* Fix formatting/alignment issues
This commit is contained in:
TSRBerry 2023-02-09 02:24:32 +01:00 • committed by GitHub
parent b3f0978869
commit ec8d4f3af5
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64 changed files with 2276 additions and 3576 deletions
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40
Ryujinx.Tests/Cpu/CpuTestBfm.cs
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@ -9,17 +9,15 @@ namespace Ryujinx.Tests.Cpu
{
#if Bfm
private const int RndCnt = 2;
private const int RndCntImmr = 2;
private const int RndCntImms = 2;
[Test, Pairwise, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
public void Bfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Random(RndCnt)] ulong xd,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0u, 31u, 32u, 63u)] uint immr,
[Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0xB3400000; // BFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Random(RndCnt)] uint wd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u)] uint immr,
[Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x33000000; // BFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -56,9 +54,9 @@ namespace Ryujinx.Tests.Cpu
public void Sbfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0u, 31u, 32u, 63u)] uint immr,
[Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0x93400000; // SBFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -75,9 +73,9 @@ namespace Ryujinx.Tests.Cpu
public void Sbfm_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u)] uint immr,
[Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x13000000; // SBFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -94,9 +92,9 @@ namespace Ryujinx.Tests.Cpu
public void Ubfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0u, 31u, 32u, 63u)] uint immr,
[Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0xD3400000; // UBFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -113,9 +111,9 @@ namespace Ryujinx.Tests.Cpu
public void Ubfm_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u)] uint immr,
[Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x53000000; // UBFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -129,4 +127,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
}
}