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Replace unicorn bindings with Nuget package (#4378)

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* Replace unicorn bindings with Nuget package

* Use nameof for ValueSource args

* Remove redundant code from test projects

* Fix wrong values for EmuStart()

Add notes to address this later again

* Improve formatting

* Fix formatting/alignment issues
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TSRBerry 2023-02-09 02:24:32 +01:00 • committed by GitHub
parent b3f0978869
commit ec8d4f3af5
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141
Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
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@ -1,9 +1,7 @@
#define SimdCvt
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
@ -17,14 +15,14 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Types)"
private static uint[] _W_()
{
return new uint[] { 0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu };
return new[] { 0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu };
}
private static ulong[] _X_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static IEnumerable<ulong> _1S_F_WX_()
@ -89,13 +87,13 @@ namespace Ryujinx.Tests.Cpu
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
(float)((int)TestContext.CurrentContext.Random.NextUInt()));
(int)TestContext.CurrentContext.Random.NextUInt());
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
(float)((long)TestContext.CurrentContext.Random.NextULong()));
(long)TestContext.CurrentContext.Random.NextULong());
ulong rnd3 = (uint)BitConverter.SingleToInt32Bits(
(float)((uint)TestContext.CurrentContext.Random.NextUInt()));
TestContext.CurrentContext.Random.NextUInt());
ulong rnd4 = (uint)BitConverter.SingleToInt32Bits(
(float)((ulong)TestContext.CurrentContext.Random.NextULong()));
TestContext.CurrentContext.Random.NextULong());
ulong rnd5 = GenNormalS();
ulong rnd6 = GenSubnormalS();
@ -170,13 +168,13 @@ namespace Ryujinx.Tests.Cpu
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((int)TestContext.CurrentContext.Random.NextUInt()));
(int)TestContext.CurrentContext.Random.NextUInt());
ulong rnd2 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((long)TestContext.CurrentContext.Random.NextULong()));
(long)TestContext.CurrentContext.Random.NextULong());
ulong rnd3 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((uint)TestContext.CurrentContext.Random.NextUInt()));
TestContext.CurrentContext.Random.NextUInt());
ulong rnd4 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((ulong)TestContext.CurrentContext.Random.NextULong()));
TestContext.CurrentContext.Random.NextULong());
ulong rnd5 = GenNormalD();
ulong rnd6 = GenSubnormalD();
@ -195,7 +193,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _F_Cvt_AMPZ_SU_Gp_SW_()
{
return new uint[]
return new[]
{
0x1E240000u, // FCVTAS W0, S0
0x1E250000u, // FCVTAU W0, S0
@ -211,7 +209,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_AMPZ_SU_Gp_SX_()
{
return new uint[]
return new[]
{
0x9E240000u, // FCVTAS X0, S0
0x9E250000u, // FCVTAU X0, S0
@ -227,7 +225,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_AMPZ_SU_Gp_DW_()
{
return new uint[]
return new[]
{
0x1E640000u, // FCVTAS W0, D0
0x1E650000u, // FCVTAU W0, D0
@ -243,7 +241,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_AMPZ_SU_Gp_DX_()
{
return new uint[]
return new[]
{
0x9E640000u, // FCVTAS X0, D0
0x9E650000u, // FCVTAU X0, D0
@ -259,7 +257,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SW_()
{
return new uint[]
return new[]
{
0x1E188000u, // FCVTZS W0, S0, #32
0x1E198000u // FCVTZU W0, S0, #32
@ -268,7 +266,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SX_()
{
return new uint[]
return new[]
{
0x9E180000u, // FCVTZS X0, S0, #64
0x9E190000u // FCVTZU X0, S0, #64
@ -277,7 +275,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DW_()
{
return new uint[]
return new[]
{
0x1E588000u, // FCVTZS W0, D0, #32
0x1E598000u // FCVTZU W0, D0, #32
@ -286,7 +284,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DX_()
{
return new uint[]
return new[]
{
0x9E580000u, // FCVTZS X0, D0, #64
0x9E590000u // FCVTZU X0, D0, #64
@ -295,7 +293,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_WS_()
{
return new uint[]
return new[]
{
0x1E220000u, // SCVTF S0, W0
0x1E230000u // UCVTF S0, W0
@ -304,7 +302,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_WD_()
{
return new uint[]
return new[]
{
0x1E620000u, // SCVTF D0, W0
0x1E630000u // UCVTF D0, W0
@ -313,7 +311,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_XS_()
{
return new uint[]
return new[]
{
0x9E220000u, // SCVTF S0, X0
0x9E230000u // UCVTF S0, X0
@ -322,7 +320,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_XD_()
{
return new uint[]
return new[]
{
0x9E620000u, // SCVTF D0, X0
0x9E630000u // UCVTF D0, X0
@ -331,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_Fixed_WS_()
{
return new uint[]
return new[]
{
0x1E028000u, // SCVTF S0, W0, #32
0x1E038000u // UCVTF S0, W0, #32
@ -340,7 +338,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_Fixed_WD_()
{
return new uint[]
return new[]
{
0x1E428000u, // SCVTF D0, W0, #32
0x1E438000u // UCVTF D0, W0, #32
@ -349,7 +347,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_Fixed_XS_()
{
return new uint[]
return new[]
{
0x9E020000u, // SCVTF S0, X0, #64
0x9E030000u // UCVTF S0, X0, #64
@ -358,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_Gp_Fixed_XD_()
{
return new uint[]
return new[]
{
0x9E420000u, // SCVTF D0, X0, #64
0x9E430000u // UCVTF D0, X0, #64
@ -367,17 +365,16 @@ namespace Ryujinx.Tests.Cpu
#endregion
private const int RndCnt = 2;
private const int RndCntFBits = 2;
private static readonly bool NoZeros = false;
private static readonly bool NoInfs = false;
private static readonly bool NoNaNs = false;
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource("_F_Cvt_AMPZ_SU_Gp_SW_")] uint opcodes,
public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_SW_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a)
[ValueSource(nameof(_1S_F_WX_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -391,10 +388,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource("_F_Cvt_AMPZ_SU_Gp_SX_")] uint opcodes,
public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_SX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a)
[ValueSource(nameof(_1S_F_WX_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -407,10 +404,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource("_F_Cvt_AMPZ_SU_Gp_DW_")] uint opcodes,
public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_DW_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a)
[ValueSource(nameof(_1D_F_WX_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -424,10 +421,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource("_F_Cvt_AMPZ_SU_Gp_DX_")] uint opcodes,
public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_DX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a)
[ValueSource(nameof(_1D_F_WX_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -440,11 +437,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SW_")] uint opcodes,
public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_SW_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_1S_F_WX_))] ulong a,
[Values(1u, 32u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -461,11 +458,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SX_")] uint opcodes,
public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_SX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_1S_F_WX_))] ulong a,
[Values(1u, 64u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -481,11 +478,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DW_")] uint opcodes,
public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_DW_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_1D_F_WX_))] ulong a,
[Values(1u, 32u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -502,11 +499,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DX_")] uint opcodes,
public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_DX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_1D_F_WX_))] ulong a,
[Values(1u, 64u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -522,10 +519,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WS([ValueSource("_SU_Cvt_F_Gp_WS_")] uint opcodes,
public void SU_Cvt_F_Gp_WS([ValueSource(nameof(_SU_Cvt_F_Gp_WS_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
[ValueSource(nameof(_W_))] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -539,10 +536,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WD([ValueSource("_SU_Cvt_F_Gp_WD_")] uint opcodes,
public void SU_Cvt_F_Gp_WD([ValueSource(nameof(_SU_Cvt_F_Gp_WD_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
[ValueSource(nameof(_W_))] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -556,10 +553,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XS([ValueSource("_SU_Cvt_F_Gp_XS_")] uint opcodes,
public void SU_Cvt_F_Gp_XS([ValueSource(nameof(_SU_Cvt_F_Gp_XS_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
[ValueSource(nameof(_X_))] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -573,10 +570,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XD([ValueSource("_SU_Cvt_F_Gp_XD_")] uint opcodes,
public void SU_Cvt_F_Gp_XD([ValueSource(nameof(_SU_Cvt_F_Gp_XD_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
[ValueSource(nameof(_X_))] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@ -590,11 +587,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource("_SU_Cvt_F_Gp_Fixed_WS_")] uint opcodes,
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_WS_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_W_))] uint wn,
[Values(1u, 32u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -611,11 +608,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_WD([ValueSource("_SU_Cvt_F_Gp_Fixed_WD_")] uint opcodes,
public void SU_Cvt_F_Gp_Fixed_WD([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_WD_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_W_))] uint wn,
[Values(1u, 32u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -632,11 +629,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource("_SU_Cvt_F_Gp_Fixed_XS_")] uint opcodes,
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_XS_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_X_))] ulong xn,
[Values(1u, 64u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -653,11 +650,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource("_SU_Cvt_F_Gp_Fixed_XD_")] uint opcodes,
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_XD_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
[ValueSource(nameof(_X_))] ulong xn,
[Values(1u, 64u)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
@ -674,4 +671,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
}
}