Replace unicorn bindings with Nuget package (#4378)
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
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64 changed files with 2276 additions and 3576 deletions
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@ -1,9 +1,7 @@
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#define SimdImm
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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@ -50,14 +48,14 @@ namespace Ryujinx.Tests.Cpu
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<byte> _8BIT_IMM_()
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@ -94,7 +92,7 @@ namespace Ryujinx.Tests.Cpu
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#region "ValueSource (Opcodes)"
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private static uint[] _Bic_Orr_Vi_16bit_()
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{
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return new uint[]
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return new[]
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{
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0x2F009400u, // BIC V0.4H, #0
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0x0F009400u // ORR V0.4H, #0
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@ -103,7 +101,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Bic_Orr_Vi_32bit_()
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{
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return new uint[]
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return new[]
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{
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0x2F001400u, // BIC V0.2S, #0
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0x0F001400u // ORR V0.2S, #0
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@ -112,7 +110,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _F_Mov_Vi_2S_()
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{
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return new uint[]
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return new[]
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{
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0x0F00F400u // FMOV V0.2S, #2.0
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};
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@ -120,7 +118,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _F_Mov_Vi_4S_()
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{
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return new uint[]
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return new[]
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{
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0x4F00F400u // FMOV V0.4S, #2.0
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};
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@ -128,7 +126,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _F_Mov_Vi_2D_()
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{
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return new uint[]
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return new[]
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{
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0x6F00F400u // FMOV V0.2D, #2.0
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};
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@ -136,7 +134,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_V_8bit_()
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{
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return new uint[]
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return new[]
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{
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0x0F00E400u // MOVI V0.8B, #0
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};
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@ -144,7 +142,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_Mvni_V_16bit_shifted_imm_()
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{
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return new uint[]
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return new[]
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{
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0x0F008400u, // MOVI V0.4H, #0
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0x2F008400u // MVNI V0.4H, #0
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@ -153,7 +151,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_Mvni_V_32bit_shifted_imm_()
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{
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return new uint[]
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return new[]
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{
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0x0F000400u, // MOVI V0.2S, #0
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0x2F000400u // MVNI V0.2S, #0
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@ -162,7 +160,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_Mvni_V_32bit_shifting_ones_()
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{
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return new uint[]
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return new[]
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{
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0x0F00C400u, // MOVI V0.2S, #0, MSL #8
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0x2F00C400u // MVNI V0.2S, #0, MSL #8
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@ -171,7 +169,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_V_64bit_scalar_()
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{
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return new uint[]
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return new[]
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{
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0x2F00E400u // MOVI D0, #0
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};
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@ -179,21 +177,20 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Movi_V_64bit_vector_()
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{
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return new uint[]
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return new[]
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{
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0x6F00E400u // MOVI V0.2D, #0
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};
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntImm8 = 2;
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private const int RndCntImm64 = 2;
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[Test, Pairwise]
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public void Bic_Orr_Vi_16bit([ValueSource("_Bic_Orr_Vi_16bit_")] uint opcodes,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Bic_Orr_Vi_16bit([ValueSource(nameof(_Bic_Orr_Vi_16bit_))] uint opcodes,
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[ValueSource(nameof(_4H_))] ulong z,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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@ -212,9 +209,9 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Bic_Orr_Vi_32bit([ValueSource("_Bic_Orr_Vi_32bit_")] uint opcodes,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Bic_Orr_Vi_32bit([ValueSource(nameof(_Bic_Orr_Vi_32bit_))] uint opcodes,
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[ValueSource(nameof(_2S_))] ulong z,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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@ -233,7 +230,7 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2S([ValueSource("_F_Mov_Vi_2S_")] uint opcodes,
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public void F_Mov_Vi_2S([ValueSource(nameof(_F_Mov_Vi_2S_))] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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@ -250,7 +247,7 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_4S([ValueSource("_F_Mov_Vi_4S_")] uint opcodes,
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public void F_Mov_Vi_4S([ValueSource(nameof(_F_Mov_Vi_4S_))] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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@ -264,7 +261,7 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2D([ValueSource("_F_Mov_Vi_2D_")] uint opcodes,
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public void F_Mov_Vi_2D([ValueSource(nameof(_F_Mov_Vi_2D_))] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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@ -278,8 +275,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_V_8bit([ValueSource("_Movi_V_8bit_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Movi_V_8bit([ValueSource(nameof(_Movi_V_8bit_))] uint opcodes,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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@ -297,8 +294,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_16bit_shifted_imm([ValueSource("_Movi_Mvni_V_16bit_shifted_imm_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Movi_Mvni_V_16bit_shifted_imm([ValueSource(nameof(_Movi_Mvni_V_16bit_shifted_imm_))] uint opcodes,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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@ -318,8 +315,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifted_imm([ValueSource("_Movi_Mvni_V_32bit_shifted_imm_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Movi_Mvni_V_32bit_shifted_imm([ValueSource(nameof(_Movi_Mvni_V_32bit_shifted_imm_))] uint opcodes,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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@ -339,8 +336,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifting_ones([ValueSource("_Movi_Mvni_V_32bit_shifting_ones_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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public void Movi_Mvni_V_32bit_shifting_ones([ValueSource(nameof(_Movi_Mvni_V_32bit_shifting_ones_))] uint opcodes,
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[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <8, 16>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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@ -360,8 +357,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_V_64bit_scalar([ValueSource("_Movi_V_64bit_scalar_")] uint opcodes,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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public void Movi_V_64bit_scalar([ValueSource(nameof(_Movi_V_64bit_scalar_))] uint opcodes,
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[ValueSource(nameof(_64BIT_IMM_))] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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@ -379,8 +376,8 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Movi_V_64bit_vector([ValueSource("_Movi_V_64bit_vector_")] uint opcodes,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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public void Movi_V_64bit_vector([ValueSource(nameof(_Movi_V_64bit_vector_))] uint opcodes,
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[ValueSource(nameof(_64BIT_IMM_))] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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@ -395,4 +392,4 @@ namespace Ryujinx.Tests.Cpu
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}
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#endif
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}
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}
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}
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