Replace unicorn bindings with Nuget package (#4378)
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
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TSRBerry
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64 changed files with 2276 additions and 3576 deletions
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@ -13,33 +13,30 @@ namespace Ryujinx.Tests.Cpu
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#region "ValueSource (Types)"
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Vshr_Imm_SU8_()
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{
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return new uint[]
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return new[]
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{
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0xf2880010u, // VSHR.S8 D0, D0, #8
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0xf2880110u, // VSRA.S8 D0, D0, #8
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@ -50,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Vshr_Imm_SU16_()
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{
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return new uint[]
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return new[]
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{
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0xf2900010u, // VSHR.S16 D0, D0, #16
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0xf2900110u, // VSRA.S16 D0, D0, #16
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@ -61,7 +58,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Vshr_Imm_SU32_()
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{
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return new uint[]
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return new[]
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{
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0xf2a00010u, // VSHR.S32 D0, D0, #32
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0xf2a00110u, // VSRA.S32 D0, D0, #32
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@ -72,7 +69,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Vshr_Imm_SU64_()
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{
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return new uint[]
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return new[]
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{
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0xf2800190u, // VSRA.S64 D0, D0, #64
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0xf2800290u, // VRSHR.S64 D0, D0, #64
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@ -82,7 +79,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Vqshrn_Vqrshrn_Vrshrn_Imm_()
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{
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return new uint[]
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return new[]
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{
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0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN)
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0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN)
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@ -92,7 +89,7 @@ namespace Ryujinx.Tests.Cpu
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private static uint[] _Vqshrun_Vqrshrun_Imm_()
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{
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return new uint[]
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return new[]
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{
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0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN)
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0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
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@ -104,12 +101,12 @@ namespace Ryujinx.Tests.Cpu
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private const int RndCntShiftImm = 2;
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[Test, Pairwise]
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public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
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public void Vshr_Imm_SU8([ValueSource(nameof(_Vshr_Imm_SU8_))] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
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[Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong b,
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[Values(1u, 8u)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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@ -119,12 +116,12 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
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public void Vshr_Imm_SU16([ValueSource(nameof(_Vshr_Imm_SU16_))] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
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[ValueSource(nameof(_4H_))] ulong z,
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[ValueSource(nameof(_4H_))] ulong b,
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[Values(1u, 16u)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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@ -134,12 +131,12 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
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public void Vshr_Imm_SU32([ValueSource(nameof(_Vshr_Imm_SU32_))] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
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[ValueSource(nameof(_2S_))] ulong z,
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[ValueSource(nameof(_2S_))] ulong b,
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[Values(1u, 32u)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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@ -149,12 +146,12 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
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public void Vshr_Imm_SU64([ValueSource(nameof(_Vshr_Imm_SU64_))] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong b,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
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[ValueSource(nameof(_1D_))] ulong z,
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[ValueSource(nameof(_1D_))] ulong b,
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[Values(1u, 64u)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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@ -195,7 +192,7 @@ namespace Ryujinx.Tests.Cpu
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public void Vshl_Imm([Values(0u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u, 3u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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@ -229,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
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public void Vshrn_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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@ -253,11 +250,11 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource("_Vqshrn_Vqrshrn_Vrshrn_Imm_")] uint opcode,
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public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource(nameof(_Vqshrn_Vqrshrn_Vrshrn_Imm_))] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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@ -287,11 +284,11 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vqshrun_Vqrshrun_Imm([ValueSource("_Vqshrun_Vqrshrun_Imm_")] uint opcode,
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public void Vqshrun_Vqrshrun_Imm([ValueSource(nameof(_Vqshrun_Vqrshrun_Imm_))] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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@ -315,4 +312,4 @@ namespace Ryujinx.Tests.Cpu
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}
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#endif
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}
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}
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}
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