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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

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* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
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gdkchan 2022-01-21 12:47:34 -03:00 • committed by GitHub
parent 7e967d796c
commit f0824fde9f
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6 changed files with 21 additions and 5 deletions
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4
ARMeilleure/Instructions/InstEmitMemoryEx.cs
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@ -167,9 +167,7 @@ namespace ARMeilleure.Instructions
private static void EmitBarrier(ArmEmitterContext context)
{
// Note: This barrier is most likely not necessary, and probably
// doesn't make any difference since we need to do a ton of stuff
// (software MMU emulation) to read or write anything anyway.
context.MemoryBarrier();
}
}
}