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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

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* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
This commit is contained in:
gdkchan 2022-01-21 12:47:34 -03:00 • committed by GitHub
parent 7e967d796c
commit f0824fde9f
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GPG key ID: 4AEE18F83AFDEB23
6 changed files with 21 additions and 5 deletions
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5
ARMeilleure/Translation/EmitterContext.cs
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@ -325,6 +325,11 @@ namespace ARMeilleure.Translation
Add(Instruction.LoadFromContext);
}
public void MemoryBarrier()
{
Add(Instruction.MemoryBarrier);
}
public Operand Multiply(Operand op1, Operand op2)
{
return Add(Instruction.Multiply, Local(op1.Type), op1, op2);

2
ARMeilleure/Translation/PTC/Ptc.cs
View file

@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
private const string OuterHeaderMagicString = "PTCohd\0\0";
private const string InnerHeaderMagicString = "PTCihd\0\0";
private const uint InternalVersion = 2953; //! To be incremented manually for each change to the ARMeilleure project.
private const uint InternalVersion = 3015; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";