Implement Ssubw_V and Usubw_V instructions. (#287)
* Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdCmp.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
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8 changed files with 620 additions and 35 deletions
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@ -3315,6 +3315,37 @@ namespace Ryujinx.Tests.Cpu.Tester
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Vpart(d, part, result);
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}
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// xtn_advsimd.html
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public static void Xtn_V(bool Q, Bits size, Bits Rn, Bits Rd)
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{
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/* Decode Vector */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(datasize);
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Bits operand = V(2 * datasize, n);
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Bits element;
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for (int e = 0; e <= elements - 1; e++)
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{
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element = Elem(operand, e, 2 * esize);
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Elem(result, e, esize, element[esize - 1, 0]);
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}
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Vpart(d, part, result);
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}
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#endregion
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#region "SimdReg"
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@ -4395,8 +4426,8 @@ namespace Ryujinx.Tests.Cpu.Tester
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool unsigned = (U == true);
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bool accumulate = (op == false);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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@ -4484,8 +4515,8 @@ namespace Ryujinx.Tests.Cpu.Tester
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool unsigned = (U == true);
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bool accumulate = (op == false);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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@ -4511,6 +4542,108 @@ namespace Ryujinx.Tests.Cpu.Tester
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V(d, result);
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}
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// saddw_advsimd.html
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public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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const bool U = false;
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const bool o1 = false;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool sub_op = (o1 == true);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(2 * datasize);
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Bits operand1 = V(2 * datasize, n);
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Bits operand2 = Vpart(datasize, m, part);
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BigInteger element1;
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BigInteger element2;
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BigInteger sum;
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for (int e = 0; e <= elements - 1; e++)
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{
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element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
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element2 = Int(Elem(operand2, e, esize), unsigned);
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if (sub_op)
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{
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sum = element1 - element2;
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}
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else
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{
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sum = element1 + element2;
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}
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Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
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}
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V(d, result);
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}
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// ssubw_advsimd.html
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public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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const bool U = false;
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const bool o1 = true;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool sub_op = (o1 == true);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(2 * datasize);
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Bits operand1 = V(2 * datasize, n);
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Bits operand2 = Vpart(datasize, m, part);
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BigInteger element1;
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BigInteger element2;
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BigInteger sum;
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for (int e = 0; e <= elements - 1; e++)
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{
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element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
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element2 = Int(Elem(operand2, e, esize), unsigned);
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if (sub_op)
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{
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sum = element1 - element2;
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}
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else
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{
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sum = element1 + element2;
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}
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Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
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}
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V(d, result);
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}
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// sub_advsimd.html#SUB_asisdsame_only
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public static void Sub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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@ -4785,8 +4918,8 @@ namespace Ryujinx.Tests.Cpu.Tester
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool unsigned = (U == true);
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bool accumulate = (op == false);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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@ -4874,8 +5007,8 @@ namespace Ryujinx.Tests.Cpu.Tester
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool unsigned = (U == true);
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bool accumulate = (op == false);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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@ -4901,6 +5034,108 @@ namespace Ryujinx.Tests.Cpu.Tester
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V(d, result);
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}
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// uaddw_advsimd.html
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public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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const bool U = true;
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const bool o1 = false;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool sub_op = (o1 == true);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(2 * datasize);
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Bits operand1 = V(2 * datasize, n);
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Bits operand2 = Vpart(datasize, m, part);
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BigInteger element1;
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BigInteger element2;
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BigInteger sum;
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for (int e = 0; e <= elements - 1; e++)
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{
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element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
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element2 = Int(Elem(operand2, e, esize), unsigned);
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if (sub_op)
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{
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sum = element1 - element2;
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}
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else
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{
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sum = element1 + element2;
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}
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Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
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}
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V(d, result);
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}
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// usubw_advsimd.html
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public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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const bool U = true;
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const bool o1 = true;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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bool sub_op = (o1 == true);
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bool unsigned = (U == true);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(2 * datasize);
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Bits operand1 = V(2 * datasize, n);
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Bits operand2 = Vpart(datasize, m, part);
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BigInteger element1;
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BigInteger element2;
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BigInteger sum;
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for (int e = 0; e <= elements - 1; e++)
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{
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element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
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element2 = Int(Elem(operand2, e, esize), unsigned);
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if (sub_op)
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{
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sum = element1 - element2;
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}
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else
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{
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sum = element1 + element2;
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}
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Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
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}
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V(d, result);
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}
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// uzp1_advsimd.html
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public static void Uzp1_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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